SN74LV6T07

Name: SN74LV6T07
Brand: TI
SKU: SN74LV6T07
Price: 0.2 USD

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6-Bit-Puffer für Einzelstromversorgung mit 1,8 bis 5,5 V und Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN74LV6T07 Hex Open-Drain Buffers with Integrated Translation datasheet (Englisch) PDF | HTML

SN74LV6T07

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Technology family

LV1T

Applications

GPIO, SPI

Bits (#)

Configuration

6 Ch A to B 0 Ch B to A

High input voltage (min) (V)

High input voltage (max) (V)

5.5

Vout (min) (V)

1.65

Vout (max) (V)

5.5

Data rate (max) (Mbps)

200

IOH (max) (mA)

-8

IOL (max) (mA)

Features

Balanced outputs, Single supply

Input type

TTL-Compatible CMOS

Output type

Balanced CMOS, Open-drain

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LV1T

Applications

GPIO, SPI

Bits (#)

Configuration

6 Ch A to B 0 Ch B to A

High input voltage (min) (V)

High input voltage (max) (V)

5.5

Vout (min) (V)

1.65

Vout (max) (V)

5.5

Data rate (max) (Mbps)

200

IOH (max) (mA)

-8

IOL (max) (mA)

Features

Balanced outputs, Single supply

Input type

TTL-Compatible CMOS

Output type

Balanced CMOS, Open-drain

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (PW)

32 mm² 5 x 6.4

WQFN (BQA)

7.5 mm² 3 x 2.5

Wide operating range of 1.65 V to 5.5 V
5.5-V tolerant input pins
LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
- Over 6.67-Mbps operation, (R PU = 1 kΩ, C L = 30 pF)
- Up translation from 1.2 V to 5 V with 1.8-V supply
- Down translation from 5 V to 0.8 V or even less with any valid supply
5.5-V tolerant input pins
Supports standard function pinout
Latch-up performance exceeds 250 mA per JESD 17

Wide operating range of 1.65 V to 5.5 V
5.5-V tolerant input pins
LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
- Over 6.67-Mbps operation, (R PU = 1 kΩ, C L = 30 pF)
- Up translation from 1.2 V to 5 V with 1.8-V supply
- Down translation from 5 V to 0.8 V or even less with any valid supply
5.5-V tolerant input pins
Supports standard function pinout
Latch-up performance exceeds 250 mA per JESD 17

The SN74LV6T07 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV6T07 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.

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Technische Dokumentation

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*	Data sheet	SN74LV6T07 Hex Open-Drain Buffers with Integrated Translation datasheet	PDF \| HTML	21 Aug 2023
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Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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