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Microcontroladores (MCU) y procesadores
Procesadores basados en Arm

66AK2H06

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DSP+Arm multinúcleo de alto rendimiento: 2x Arm, núcleos A15, 4x C66x DSP núcleos

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66AK2H06

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Detalles del producto

Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1200, 1400 Coprocessors C66x DSP CPU 32-bit Protocols Ethernet Ethernet MAC 4-Port 1Gb switch PCIe 2 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Device identity, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1200, 1400 Coprocessors C66x DSP CPU 32-bit Protocols Ethernet Ethernet MAC 4-Port 1Gb switch PCIe 2 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Device identity, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (AAW) 1517 1600 mm² 40 x 40
  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC
  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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Documentación técnica

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* Data sheet 66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC) datasheet (Rev. G) PDF | HTML 09 oct 2017
* Errata 66AK2Hxx Multicore DSP+ARM KeyStone II SOC Errata (Revs 1.0, 1.1, 2.0, 3.0, 3.1) (Rev. F) 05 jun 2018
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 30 mar 2023
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 30 mar 2023
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 07 jul 2022
Application note Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B) PDF | HTML 07 sep 2021
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 25 jun 2021
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 may 2021
Application note Implementing an FTP Server on TI 66AK2H Device With RTOS PDF | HTML 17 ago 2020
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 11 jun 2019
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 04 jun 2019
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 03 jun 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 03 jun 2019
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 17 may 2019
Application note KeyStone II DDR3 interface bring-up 07 mar 2019
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 19 nov 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 19 nov 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 16 ene 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 16 ene 2018
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 30 sep 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 30 sep 2017
Application note Power Consumption Summary for 66AK2Hx System-on-Chip (SoC) Device Family 28 sep 2017
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 21 ago 2017
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14 ago 2017
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26 jul 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 21 jun 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 21 jun 2017
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 27 jul 2016
Application note Power Management of KS2 Device (Rev. C) 15 jul 2016
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 30 abr 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 30 abr 2016
Application note SERDES Link Commissioning on KeyStone I and II Devices 13 abr 2016
White paper Multicore SoCs stay a step ahead of SoC FPGAs 23 feb 2016
Application note TI DSP Benchmarking 13 ene 2016
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 22 dic 2015
Application note Keystone II DDR3 Debug Guide 16 oct 2015
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 06 may 2015
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 09 abr 2015
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 27 mar 2015
White paper TI’s processors leading the way in embedded analytics 03 mar 2015
Application note Keystone II DDR3 Initialization 26 ene 2015
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 05 nov 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 05 nov 2014
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 04 sep 2014
User guide Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) 03 sep 2014
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface 25 ago 2014
Application note Hardware Design Guide for KeyStone II Devices 24 mar 2014
Product overview 66AK2Hx KeyStone Multicore DSP+ARM System-on-chips (Rev. A) 08 nov 2013
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 30 sep 2013
User guide Debug and Trace for KeyStone II Devices User's Guide 26 jul 2013
User guide ARM Bootloader User Guide for KeyStone II Devices 21 jul 2013
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 15 jul 2013
User guide Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D) 03 jul 2013
User guide C66x CorePac User's Guide (Rev. C) 28 jun 2013
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28 jun 2013
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 28 may 2013
User guide Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B) 05 feb 2013
Product overview Multicore DSPs for High-Performance Video Coding 22 ene 2013
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 12 nov 2012
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 09 nov 2012
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 09 nov 2012
User guide ARM CorePac User Guide for KeyStone II Devices 31 oct 2012
Application note Multicore Programming Guide (Rev. B) 29 ago 2012
User guide Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A) 11 jul 2012
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30 mar 2012
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27 mar 2012
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22 mar 2012
Application note PCIe Use Cases for KeyStone Devices 13 dic 2011
Application note Introduction to TMS320C6000 DSP Optimization 06 oct 2011
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 02 sep 2011
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24 may 2011
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 19 may 2011
User guide C66x CPU and Instruction Set Reference Guide 09 nov 2010
User guide C66x DSP Cache User's Guide 09 nov 2010
Application note Clocking Design Guide for KeyStone Devices 09 nov 2010
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 09 nov 2010
Application note Optimizing Loops on the C66x DSP 09 nov 2010
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 09 nov 2010
User guide Network Coprocessor for KeyStone Devices User's Guide 02 nov 2010

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Sonda de depuración

TMDSEMU200-U — Sonda de depuración XDS200 USB

El XDS200 es una sonda de depuración (emulador) que se utiliza para depurar dispositivos integrados de TI. El XDS200 presenta un equilibrio de bajo costo con buen rendimiento en comparación con el XDS110 de bajo costo y el XDS560v2 de alto rendimiento. Es compatible con una amplia (...)

No disponible en TI.com
Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com
Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com
Kit de desarrollo de software (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-RTOS-K2HK — RTOS Processor SDK for K2H

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Controlador o biblioteca

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The Texas Instruments FFT library is an optimized floating-point math function library for computing the discrete Fourier transform (DFT).
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MATHLIB — Biblioteca matemática DSP para dispositivos de punto flotante

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IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

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Revise la página de detalles del producto para verificar la compatibilidad.
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Modelo de simulación

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Esquema

66AK2H14 66AK2H12 66AK2H106 AAW OrCAD Symbols

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Diseños de referencia

TIDEP0045 — Diseño de referencia de implementación de un algoritmo de radar de apertura sintética (SAR) en tiemp

This reference design shows a real-time synthetic aperture radar (SAR) running on a multicore TMS320C6678 digital signal processor (DSP). One of the main challenges of  SAR is to generate high-resolution images in real-time, since forming the image involves computationally-demanding signal (...)
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FCBGA (AAW) 1517 Ultra Librarian
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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