Detalles del producto

Function General-purpose timer Iq (typ) (mA) 2 Rating Catalog Operating temperature range (°C) 0 to 70 Supply voltage (max) (V) 16 Supply voltage (min) (V) 4.5
Function General-purpose timer Iq (typ) (mA) 2 Rating Catalog Operating temperature range (°C) 0 to 70 Supply voltage (max) (V) 16 Supply voltage (min) (V) 4.5
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6 SOP (PS) 8 48.36 mm² 6.2 x 7.8 TSSOP (PW) 8 19.2 mm² 3 x 6.4
  • Timing From Microseconds to Hours
  • Astable or Monostable Operation
  • Adjustable Duty Cycle
  • TTL-Compatible Output Can Sink or Source
    Up to 200 mA
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include
    Testing of All Parameters.
  • Timing From Microseconds to Hours
  • Astable or Monostable Operation
  • Adjustable Duty Cycle
  • TTL-Compatible Output Can Sink or Source
    Up to 200 mA
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include
    Testing of All Parameters.

These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.

The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.

The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.

These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.

The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.

The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.

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* Data sheet xx555 Precision Timers datasheet (Rev. I) PDF | HTML 15 sep 2014
Application note Considering TI Smart DACs As an Alternative to 555 Timers PDF | HTML 02 sep 2021
Technical article Using dual high-current op amps to drive automotive LED lights PDF | HTML 20 jul 2015

Diseño y desarrollo

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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
PDIP (P) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
SOP (PS) 8 Ultra Librarian
TSSOP (PW) 8 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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