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PCA9518

ACTIVO

Búfer/hub I2C/SMBus de 400 kHz bidireccional de 3 a 3,6 V ampliable de 5 canales

Detalles del producto

Features Reset pin Protocols I2C Frequency (max) (MHz) 0.4 VCCA (min) (V) 3 VCCA (max) (V) 3.6 VCCB (min) (V) 3 VCCB (max) (V) 3.6 Supply restrictions VCC Single Supply Rating Catalog Operating temperature range (°C) -40 to 85
Features Reset pin Protocols I2C Frequency (max) (MHz) 0.4 VCCA (min) (V) 3 VCCA (max) (V) 3.6 VCCB (min) (V) 3 VCCB (max) (V) 3.6 Supply restrictions VCC Single Supply Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SSOP (DB) 20 56.16 mm² 7.2 x 7.8 SSOP (DBQ) 20 51.9 mm² 8.65 x 6 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Expandable Five-Channel Bidirectional Buffer
  • 400-kHz Fast I2C Bus
  • Operating VCC Range of 3 V to 3.6 V
  • 5-V Tolerant I2C and Enable Input Pins to Support Mixed-Mode Signal Operation
  • Active-High Individual Repeater Enable Inputs
  • Open-Drain Input/Outputs
  • Lockup-Free Operation
  • Supports Multiple Masters
  • Powered-Off High-Impedance I2C Pins
  • I2C Bus and SMBus Compatible
  • Latchup Performance Exceeds 100 mA Per JESD 78
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

  • Expandable Five-Channel Bidirectional Buffer
  • 400-kHz Fast I2C Bus
  • Operating VCC Range of 3 V to 3.6 V
  • 5-V Tolerant I2C and Enable Input Pins to Support Mixed-Mode Signal Operation
  • Active-High Individual Repeater Enable Inputs
  • Open-Drain Input/Outputs
  • Lockup-Free Operation
  • Supports Multiple Masters
  • Powered-Off High-Impedance I2C Pins
  • I2C Bus and SMBus Compatible
  • Latchup Performance Exceeds 100 mA Per JESD 78
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

The PCA9518 is an expandable five-channel bidirectional buffer for I2C and SMBus applications. The I2C protocol requires a maximum bus capacitance of 400 pF, which is derived from the number of devices on the I2C bus and the bus length. The PCA9518 overcomes this restriction by separating and buffering the I2C data (SDA) and clock (SCL) lines into multiple groups of 400-pF segments. Any segment-to-segment transition sees only one repeater delay. Each PCA9518 can communicate with other PCA9518 hubs through a 4-wire inter-hub expansion bus. Using multiple PCA9518 parts, any width hub (in multiples of five) can be implemented using the expansion pins, with only one repeater delay and no functional degradation of the system performance.

The PCA9518 does not support clock stretching across the repeater.

The device is designed for 3-V to 3.6-V VCC operation, but it has 5-V tolerant I2C and enable (EN) input pins. This feature allows for translation from 3 V to 5 V between a master and slave. The enable pin also can be used to electrically isolate a repeater segment from the I2C bus. This is useful in cases where one segment needs to run at 100 kHz while the rest of the system is at 400 kHz. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz, because of the delays added by the repeater.

The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents a lockup condition from occurring when the input low condition is released.

A PCA9518 cluster cannot be put in series with a repeater such as the PCA9515 or another PCA9518 cluster, as the design does not allow this configuration. Multiple PCA9518 devices can be grouped with other PCA9518 devices into any size cluster using the EXPxxxx pins that allow the I2C signals to be sent or received from one PCA9518 to another PCA9518 within the cluster. Because there is no direction pin, slightly different valid low voltage levels are used to avoid lockup conditions between the input and the output of individual repeaters in the cluster. A valid low applied at the input of any of the PCA9518 devices is propagated as a buffered low, with a slightly higher value, to all enabled outputs in the PCA9518 cluster. When this buffered low is applied to another repeater or separate PCA9518 cluster (not connected via the EXPxxxx pins) in series, the second repeater or PCA9518 cluster does not recognize it as a regular low and does not propagate it as a buffered low again. For this reason, the PCA9518 should not be put in series with other repeater or PCA9518 clusters.

The PCA9518 has five multidirectional open-drain buffers designed to support the standard low-level-contention arbitration of the I2C bus. Except during arbitration, the PCA9518 acts like a pair of noninverting open-drain buffers, one for SDA and one for SCL.

There is an internal power-on-reset circuit (VPOR) that allows for an initial condition and the ramping of VCC to set the internal logic.

As with the standard I2C system, pullup resistors are required on each SDAn and SCLn to provide the logic high levels on the buffered bus. The size of these pullup resistors depends on the system, but it is essential that each side of the repeater have a pullup resistor. The device is designed to work with standard-mode and fast-mode I2C devices in addition to SMBus devices. Standard-mode I2C devices only specify 3 mA in a generic I2C system where standard-mode devices and multiple masters are possible.

The PCA9518 is an expandable five-channel bidirectional buffer for I2C and SMBus applications. The I2C protocol requires a maximum bus capacitance of 400 pF, which is derived from the number of devices on the I2C bus and the bus length. The PCA9518 overcomes this restriction by separating and buffering the I2C data (SDA) and clock (SCL) lines into multiple groups of 400-pF segments. Any segment-to-segment transition sees only one repeater delay. Each PCA9518 can communicate with other PCA9518 hubs through a 4-wire inter-hub expansion bus. Using multiple PCA9518 parts, any width hub (in multiples of five) can be implemented using the expansion pins, with only one repeater delay and no functional degradation of the system performance.

The PCA9518 does not support clock stretching across the repeater.

The device is designed for 3-V to 3.6-V VCC operation, but it has 5-V tolerant I2C and enable (EN) input pins. This feature allows for translation from 3 V to 5 V between a master and slave. The enable pin also can be used to electrically isolate a repeater segment from the I2C bus. This is useful in cases where one segment needs to run at 100 kHz while the rest of the system is at 400 kHz. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz, because of the delays added by the repeater.

The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents a lockup condition from occurring when the input low condition is released.

A PCA9518 cluster cannot be put in series with a repeater such as the PCA9515 or another PCA9518 cluster, as the design does not allow this configuration. Multiple PCA9518 devices can be grouped with other PCA9518 devices into any size cluster using the EXPxxxx pins that allow the I2C signals to be sent or received from one PCA9518 to another PCA9518 within the cluster. Because there is no direction pin, slightly different valid low voltage levels are used to avoid lockup conditions between the input and the output of individual repeaters in the cluster. A valid low applied at the input of any of the PCA9518 devices is propagated as a buffered low, with a slightly higher value, to all enabled outputs in the PCA9518 cluster. When this buffered low is applied to another repeater or separate PCA9518 cluster (not connected via the EXPxxxx pins) in series, the second repeater or PCA9518 cluster does not recognize it as a regular low and does not propagate it as a buffered low again. For this reason, the PCA9518 should not be put in series with other repeater or PCA9518 clusters.

The PCA9518 has five multidirectional open-drain buffers designed to support the standard low-level-contention arbitration of the I2C bus. Except during arbitration, the PCA9518 acts like a pair of noninverting open-drain buffers, one for SDA and one for SCL.

There is an internal power-on-reset circuit (VPOR) that allows for an initial condition and the ramping of VCC to set the internal logic.

As with the standard I2C system, pullup resistors are required on each SDAn and SCLn to provide the logic high levels on the buffered bus. The size of these pullup resistors depends on the system, but it is essential that each side of the repeater have a pullup resistor. The device is designed to work with standard-mode and fast-mode I2C devices in addition to SMBus devices. Standard-mode I2C devices only specify 3 mA in a generic I2C system where standard-mode devices and multiple masters are possible.

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Documentación técnica

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Tipo Título Fecha
* Data sheet PCA9518 Expandable Five-Channel I2C Hub datasheet (Rev. C) 12 jun 2014
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 jul 2024
Application note I2C Dynamic Addressing 25 abr 2019
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Choosing the Correct I2C Device for New Designs PDF | HTML 07 sep 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
Application note Understanding the I2C Bus PDF | HTML 30 jun 2015
Application note Maximum Clock Frequency of I2C Bus Using Repeaters 15 may 2015
Application note I2C Bus Pull-Up Resistor Calculation PDF | HTML 13 feb 2015
Application note Programming Fun Lights With TI's TCA6507 30 nov 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004

Diseño y desarrollo

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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (DW) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
SSOP (DBQ) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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