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SN74AUC1G86

ACTIVO

Puerta XOR (OR exclusiva) única de 2 entradas, de 0.8 V a 2.7 V, de alta velocidad

Detalles del producto

Technology family AUC Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 2.7 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 9 Input type Standard CMOS IOH (max) (mA) -9 Output type Push-Pull Features Over-voltage tolerant Inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 250 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUC Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 2.7 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 9 Input type Standard CMOS IOH (max) (mA) -9 Output type Push-Pull Features Over-voltage tolerant Inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 250 Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 5 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial Power-Down-Mode Operation
  • Sub-1-V Operable
  • Max tpd of 2.5 ns at 1.8 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

NanoFree is a trademark of Texas Instruments.

  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial Power-Down-Mode Operation
  • Sub-1-V Operable
  • Max tpd of 2.5 ns at 1.8 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

NanoFree is a trademark of Texas Instruments.

This single 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC1G86 performs the Boolean function Y = A • B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC1G86 performs the Boolean function Y = A • B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Documentación técnica

star =Principal documentación para este producto seleccionada por TI
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Tipo Título Fecha
* Data sheet SN74AUC1G86 Single 2-Input Exclusive-OR Gate datasheet (Rev. J) 20 nov 2007
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices 21 mar 2003
User guide AUC Data Book, January 2003 (Rev. A) 01 ene 2003
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
More literature AUC Product Brochure (Rev. A) 18 mar 2002

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
Modelo de simulación

SN74AUC1G86 Behavioral SPICE Model

SCEM719.ZIP (7 KB) - PSpice Model
Modelo de simulación

SN74AUC1G86 IBIS Model (Rev. B)

SCEM313B.ZIP (54 KB) - IBIS Model
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
DSBGA (YZP) 5 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

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