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Lógica y traducción de voltaje
Traductores de tensión y desplazadores de nivel
Traductores de tensión con control de dirección

SN74LVC2T45

ACTIVO

Transceptor de alimentación doble de 2 bits con selector de nivel de tensión configurable y salidas

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SN74LVC2T45

ACTIVO
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Detalles del producto

Technology family LVC Applications GPIO, I2S Bits (#) 2 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 420 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 4 Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LVC Applications GPIO, I2S Bits (#) 2 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 420 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 4 Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4-µA maximum ICC
  • Available in the Texas Instruments NanoFree™ package
  • ±24-mA output drive at 3.3 V
  • Ioff supports Partial-Power-Down mode operation
  • Maximum data rates:
    • 420 Mbps (3.3-V to 5-V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4-µA maximum ICC
  • Available in the Texas Instruments NanoFree™ package
  • ±24-mA output drive at 3.3 V
  • Ioff supports Partial-Power-Down mode operation
  • Maximum data rates:
    • 420 Mbps (3.3-V to 5-V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC2T45 is designed so that VCCA supplies the DIR input circuit. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, both ports are in the high-impedance state.

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC2T45 is designed so that VCCA supplies the DIR input circuit. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, both ports are in the high-impedance state.
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Documentación técnica

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* Data sheet SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation datasheet (Rev. N) PDF | HTML 21 jun 2024
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 jul 2024
EVM User's guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. B) 30 jul 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 abr 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
No disponible en TI.com
Placa de evaluación

AVCLVCDIRCNTRL-EVM — EVM genérico para dispositivo de traducción bidireccional controlado por dirección compatible con AV

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

Guía del usuario: PDF
No disponible en TI.com
Modelo de simulación

SN74LVC2T45 IBIS Model (Rev. A)

SCEM409A.ZIP (95 KB) - IBIS Model
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Design guide: PDF
Esquema: PDF
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Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01630 — Diseño de referencia de interfaz RS485 de alta inmunidad EMC para codificadores Tamagawa

EMC immunity, especially immunity against inverter switching noise, is important for positioning encoder feedback systems of industrial drives. This design demonstrates a high EMC immunity RS485 transceiver solution which can be used on both the drive and encoder, such as Tamagawa™, EnDat (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01401 — Diseño de referencia de la interfaz RS-485 de alta inmunidad EMC para codificadores absolutos

This high EMC immunity reference design demonstrates a RS-485 transceiver to use on both the drive and within encoders such as: EnDat 2.2, BiSS®, Tamagawa™, etc. EMC immunity, particularly immunity against inverter switching noise, is important for position encoder feedback systems (...)
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
DSBGA (YZP) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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  • Lugar de fabricación
  • Lugar de ensamblaje

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