TCA9416

ACTIVO

Traductor I2C de tensión ultra baja con aceleradores de tiempo de subida

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Hoja de datos

document-pdfAcrobat TCA9416 Ultra-Low-Voltage I2C Translator with Rise Time Accelerators datasheet (Rev. A) (Inglés) PDF | HTML

TCA9416

ACTIVO

Hoja de datos

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Detalles del producto

Features

Output Enable

Protocols

I2C

Frequency (max) (MHz)

1

VCCA (min) (V)

1.08

VCCA (max) (V)

3.6

VCCB (min) (V)

1.08

VCCB (max) (V)

3.6

Supply restrictions

No rule

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Features

Output Enable

Protocols

I2C

Frequency (max) (MHz)

1

VCCA (min) (V)

1.08

VCCA (max) (V)

3.6

VCCB (min) (V)

1.08

VCCB (max) (V)

3.6

Supply restrictions

No rule

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SOT-23-THN (DDF)

8

8.12 mm² 2.9 x 2.8

X2SON (DTM)

8

1.08 mm² 0.8 x 1.35

2-bit bidirectional translator for SDA and SCL lines in I²C applications
Provides bidirectional voltage translation with no direction pin
High-impedance output SCL_A, SDA_A, SCL_B, SDA_B pins when OE = 0 V or V_CC = 0 V
Internal 10-kΩ pull-up resistor on all SDA and SCL pins are enabled based on respective V_CC voltage
1.08 V to 3.6 V on both A and B ports
V_CC Isolation feature: If either V_CC input is at GND, both ports are in the high-impedance state (excluding pull-ups)
No power-supply sequencing required: either V_CCA or V_CCB can be ramped first
Low I_off of 2.5 µA when either V_CCA or V_CCB = 0 V
OE input can be tied directly to V_CCA or controlled by GPIO
Latch-up performance exceeds 100 mA per JESD 78, class II
ESD Protection exceeds JESD 22
- 2500-V Human-body model (A114-B)
- 1500-V Charged-device model (C101)

2-bit bidirectional translator for SDA and SCL lines in I²C applications
Provides bidirectional voltage translation with no direction pin
High-impedance output SCL_A, SDA_A, SCL_B, SDA_B pins when OE = 0 V or V_CC = 0 V
Internal 10-kΩ pull-up resistor on all SDA and SCL pins are enabled based on respective V_CC voltage
1.08 V to 3.6 V on both A and B ports
V_CC Isolation feature: If either V_CC input is at GND, both ports are in the high-impedance state (excluding pull-ups)
No power-supply sequencing required: either V_CCA or V_CCB can be ramped first
Low I_off of 2.5 µA when either V_CCA or V_CCB = 0 V
OE input can be tied directly to V_CCA or controlled by GPIO
Latch-up performance exceeds 100 mA per JESD 78, class II
ESD Protection exceeds JESD 22
- 2500-V Human-body model (A114-B)
- 1500-V Charged-device model (C101)

The TCA9416 is a 2-bit bidirectional I²C and SMBus voltage-level translator with an output enable (OE) input and rising and falling edge accelerators. It is operational from 1.08 V to 3.6 V on both the A-side and B-side. This allows the device to interface between lower and higher logic signal levels at any of the typical 1.2-V, 1.8-V, 2.5-V, and 3.3-V supply rails.

The OE input pin is referenced to V_CCA, can be tied directly to V_CCA, but it is also 3.6-V tolerant. The OE pin can also be controlled and set to a logic low to place all the SCL and SDA pins in a high-impedance state, which significantly reduces the quiescent current consumption.

Under normal I²C and SMBus configurations, the TCA9416 is compatible with standard speeds where the frequency of SCL is 100 kHz (Standard-mode), 400 kHz (Fast-mode), or 1 MHz (Fast-mode Plus).

The TCA9416 features internal 10-kΩ pull-up resistors on SCL_A, SDA_A, SCL_B, and SDA_B. Additional external pull-up resistors can be added to the bus to reduce the total pull-up resistance and speed up rising edges.

The TCA9416 is a 2-bit bidirectional I²C and SMBus voltage-level translator with an output enable (OE) input and rising and falling edge accelerators. It is operational from 1.08 V to 3.6 V on both the A-side and B-side. This allows the device to interface between lower and higher logic signal levels at any of the typical 1.2-V, 1.8-V, 2.5-V, and 3.3-V supply rails.

The OE input pin is referenced to V_CCA, can be tied directly to V_CCA, but it is also 3.6-V tolerant. The OE pin can also be controlled and set to a logic low to place all the SCL and SDA pins in a high-impedance state, which significantly reduces the quiescent current consumption.

Under normal I²C and SMBus configurations, the TCA9416 is compatible with standard speeds where the frequency of SCL is 100 kHz (Standard-mode), 400 kHz (Fast-mode), or 1 MHz (Fast-mode Plus).

The TCA9416 features internal 10-kΩ pull-up resistors on SCL_A, SDA_A, SCL_B, and SDA_B. Additional external pull-up resistors can be added to the bus to reduce the total pull-up resistance and speed up rising edges.

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Documentación técnica

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Ver todo 4

	Tipo	Título		Fecha
*	Data sheet	TCA9416 Ultra-Low-Voltage I2C Translator with Rise Time Accelerators datasheet (Rev. A)	PDF \| HTML	06 ago 2021
	Application note	Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A)	PDF \| HTML	03 jul 2024
	EVM User's guide	TCA9416 Evaluation Module	PDF \| HTML	08 mar 2021
	Certificate	TCA9416EVM EU Declaration of Conformity (DoC)		25 feb 2021

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

TCA9416EVM — TCA9416 Traductor I2C de tensión ultra baja con módulo de evaluación de aceleradores de tiempo de su

Este EVM proporciona condiciones de carga configurables a través de resistencias de subida ajustables y capacitancia del bus, lo que permite a los diseñadores probar fácilmente el rendimiento de este dispositivo en su sistema.

Guía del usuario: PDF | HTML

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Modelo de simulación

TCA9416 IBIS Model

SCPM047.ZIP (63 KB) - IBIS Model

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Herramienta de diseño

I2C-DESIGNER — Herramienta de diseño I2C

Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard (...)

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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)

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Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

Guía del usuario: PDF

View Options

Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
SOT-23-THN (DDF)	8	Ultra Librarian
X2SON (DTM)	8	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

TCA9416

Traductor I2C de tensión ultra baja con aceleradores de tiempo de subida

TCA9416

Detalles del producto

Documentación técnica

Diseño y desarrollo

TCA9416EVM — TCA9416 Traductor I2C de tensión ultra baja con módulo de evaluación de aceleradores de tiempo de su

TCA9416 IBIS Model

I2C-DESIGNER — Herramienta de diseño I2C

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

TINA-TI — Programa de simulación analógica basado en SPICE

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

Videos