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Gestión de la energía
Circuitos integrados multicanal (PMIC)

TPS65919-Q1

ACTIVO

IC de administración de potencia (PMIC) con 4 bucks y 4 LDO de 3.15 V a 5.25 V para automoción

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TPS65919-Q1

ACTIVO
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Detalles del producto

Regulated outputs (#) 8 Configurability Factory programmable, Software configurable Vin (min) (V) 3.135 Vin (max) (V) 5.25 Vout (min) (V) 0.7 Vout (max) (V) 3.3 Iout (max) (A) 7 Features Comm control, I2C control, Power good, Power sequencing TI functional safety category Functional Safety-Compliant Step-up DC/DC converter 0 Step-down DC/DC converter 4 Step-down DC/DC controller 0 Step-up DC/DC controller 0 LDO 4 Iq (typ) (mA) 0.0001 Rating Automotive Switching frequency (max) (kHz) 2700 Operating temperature range (°C) -40 to 105 Processor supplier Texas Instruments Processor name Jacinto DRA7x, Jacinto TDA3x Shutdown current (ISD) (typ) (µA) 25 Switching frequency (typ) (kHz) 2200 Product type Processor and FPGA
Regulated outputs (#) 8 Configurability Factory programmable, Software configurable Vin (min) (V) 3.135 Vin (max) (V) 5.25 Vout (min) (V) 0.7 Vout (max) (V) 3.3 Iout (max) (A) 7 Features Comm control, I2C control, Power good, Power sequencing TI functional safety category Functional Safety-Compliant Step-up DC/DC converter 0 Step-down DC/DC converter 4 Step-down DC/DC controller 0 Step-up DC/DC controller 0 LDO 4 Iq (typ) (mA) 0.0001 Rating Automotive Switching frequency (max) (kHz) 2700 Operating temperature range (°C) -40 to 105 Processor supplier Texas Instruments Processor name Jacinto DRA7x, Jacinto TDA3x Shutdown current (ISD) (typ) (µA) 25 Switching frequency (typ) (kHz) 2200 Product type Processor and FPGA
VQFN (RGZ) 48 49 mm² 7 x 7
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature Range
    • Device HBM Classification Level 2
    • Device CDM Classification Level C4B
  • System Voltage Range from 3.135 V to 5.25 V
  • Low-Power Consumption
    • 20 µA in Off Mode
    • 90 µA in Sleep Mode With Two SMPSs Active
  • Four Step-Down Switched-Mode Power Supply (SMPS) Regulators:
    • 0.7- to 3.3-V Output Range in 10- or 20-mV Steps
    • Two SMPS Regulators With 3.5-A Capability, With the Ability to Combine into 7-A Output in Dual-Phase Configuration, With Differential Remote Sensing (Output and Ground)
    • Two Other SMPS Regulators with 3-A and 1.5-A Capabilities
    • Dynamic Voltage Scaling (DVS) Control and Output Current Measurement in 3.5-A and 3-A SMPS Regulators
    • Hardware and Software Controlled Eco-mode™ Supplying up to 5 mA
    • Short-Circuit Protection
    • Power-Good Indication (Voltage and Overcurrent Indication)
    • Internal Soft-Start for In-Rush Current Limitation
    • Ability to Synchronize to External Clock between 1.7 MHz and 2.7 MHz
  • Four Low-Dropout (LDO) Linear Regulators:
    • 0 .9- to 3.3-V Output Range in 50-mV steps
    • Two With 300-mA Capability and Bypass Mode
    • One With 100-mA Capability and Capable of Low-Noise Performance up to 50 mA
    • One LDO With 200-mA Current Capability
    • Short-Circuit Protection
  • 12-Bit Sigma-Delta General-Purpose ADC (GPADC) With 8 Input Channels (2 external)
  • Thermal Monitoring With High Temperature Warning and Thermal Shutdown
  • Power Sequence Control:
    • Configurable Power-Up and Power-Down Sequences (OTP)
    • Configurable Sequences Between the SLEEP and ACTIVE State Transition (OTP)
    • Three Digital Output Signals that can be Included in the Startup Sequence
  • Selectable Control Interface:
    • One SPI for Resource Configurations and DVS Control
    • Two I2C Interfaces.
      • One Dedicated for DVS Control
      • One General Purpose I2C Interface for Resource Configuration and DVS Control
  • OTP Bit-Integrity Error Detection With Options to Proceed or Hold Power-Up Sequence and RESET_OUT Release
  • Package Option:
    • 7-mm × 7-mm 48-pin With 0.5-mm Pitch
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature Range
    • Device HBM Classification Level 2
    • Device CDM Classification Level C4B
  • System Voltage Range from 3.135 V to 5.25 V
  • Low-Power Consumption
    • 20 µA in Off Mode
    • 90 µA in Sleep Mode With Two SMPSs Active
  • Four Step-Down Switched-Mode Power Supply (SMPS) Regulators:
    • 0.7- to 3.3-V Output Range in 10- or 20-mV Steps
    • Two SMPS Regulators With 3.5-A Capability, With the Ability to Combine into 7-A Output in Dual-Phase Configuration, With Differential Remote Sensing (Output and Ground)
    • Two Other SMPS Regulators with 3-A and 1.5-A Capabilities
    • Dynamic Voltage Scaling (DVS) Control and Output Current Measurement in 3.5-A and 3-A SMPS Regulators
    • Hardware and Software Controlled Eco-mode™ Supplying up to 5 mA
    • Short-Circuit Protection
    • Power-Good Indication (Voltage and Overcurrent Indication)
    • Internal Soft-Start for In-Rush Current Limitation
    • Ability to Synchronize to External Clock between 1.7 MHz and 2.7 MHz
  • Four Low-Dropout (LDO) Linear Regulators:
    • 0 .9- to 3.3-V Output Range in 50-mV steps
    • Two With 300-mA Capability and Bypass Mode
    • One With 100-mA Capability and Capable of Low-Noise Performance up to 50 mA
    • One LDO With 200-mA Current Capability
    • Short-Circuit Protection
  • 12-Bit Sigma-Delta General-Purpose ADC (GPADC) With 8 Input Channels (2 external)
  • Thermal Monitoring With High Temperature Warning and Thermal Shutdown
  • Power Sequence Control:
    • Configurable Power-Up and Power-Down Sequences (OTP)
    • Configurable Sequences Between the SLEEP and ACTIVE State Transition (OTP)
    • Three Digital Output Signals that can be Included in the Startup Sequence
  • Selectable Control Interface:
    • One SPI for Resource Configurations and DVS Control
    • Two I2C Interfaces.
      • One Dedicated for DVS Control
      • One General Purpose I2C Interface for Resource Configuration and DVS Control
  • OTP Bit-Integrity Error Detection With Options to Proceed or Hold Power-Up Sequence and RESET_OUT Release
  • Package Option:
    • 7-mm × 7-mm 48-pin With 0.5-mm Pitch

The TPS65919-Q1 PMIC integrates four configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The device is AEC-Q100 qualified. The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains four LDOs to power low-current or low-noise domains.

The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors. The OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state.

The TPS65919-Q1 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response.

The TPS65919-Q1 PMIC integrates four configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The device is AEC-Q100 qualified. The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains four LDOs to power low-current or low-noise domains.

The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors. The OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state.

The TPS65919-Q1 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response.
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TPS65916 ACTIVO Unidad de administración de energía (PMU) para procesador This product is suitable for industrial applications and is non AEQ-100 qualified.
TPS65917-Q1 ACTIVO IC de administración de potencia (PMIC) automotriz con 5 bucks y 5 LDO de 3.15 V a 5.25 V This product has the same pinout with one more buck and LDO.

Documentación técnica

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Tipo Título Fecha
* Data sheet TPS65919-Q1 Power Management Unit (PMU) for Processor datasheet (Rev. A) PDF | HTML 20 ago 2018
Application note TPS6591x-Q1 Design Checklist (Rev. A) 06 may 2021
User guide TPS65919-Q1 and TPS65917-Q1 User's Guide to Power DRA78x, and TDA3x (Rev. E) 13 mar 2019
Application note POR Generation in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 Devices (Rev. A) 21 sep 2018
Application note TPS65917 Power Estimation Tool (Rev. B) 14 jun 2018
User guide TPS65919-Q1 and TPS65917-Q1 User's Guide to Power DRA71x, DRA79x, and TDA2E-17 (Rev. E) 07 may 2018
Application note Guide to Using the GPADC in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 de (Rev. A) 13 dic 2017
Functional safety information Safety Manual for TPS65919-Q1 Power Management Unit (PMU) 18 ago 2017
User guide TPS65919-Q1 Register Map 17 ago 2017
Application note Adaptive (Dynamic) Voltage (Frequency) Scaling – Motivation and Implementations 28 mar 2014

Diseño y desarrollo

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Placa de evaluación

TPS65917EVM — Módulo de evaluación TPS65917-Q1 de administración de energía IC

The TPS65917-Q1 device is an integrated power-management integrated circuit (PMIC) for automotive applications.  The device provides five configurable step-down converters with up to 3.5A of output current for memory, processor core, input/output (I/O), or pre-regulation of LDOs. (...)

Guía del usuario: PDF
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Diseños de referencia

TIDEP-0097 — Diseño de referencia de audio de visualización de la unidad principal básica con entrada de Jacinto™

Based on TI's Jacinto™ DRA71x processor, this automotive reference design focuses on system-level cost savings. The 6 layer design reduces PCB costs through an optimized via breakout scheme, integration of key features and an optimized power distribution network. Functionality can be added or (...)
Design guide: PDF
Esquema: PDF
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VQFN (RGZ) 48 Ultra Librarian
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