홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 범용 트랜시버
홈
로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
범용 트랜시버

SN54LVCH245A-SP

활성

3상 출력을 지원하는 8진 버스 트랜시버

지금 주문
데이터 시트

SN54LVCH245A-SP

활성
데이터 시트 지금 주문

제품 상세 정보

Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL/CMOS Output type LVTTL Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family LVC Rating Space Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL/CMOS Output type LVTTL Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family LVC Rating Space Operating temperature range (°C) -55 to 125
CDIP (J) 20 167.464 mm² 24.2 x 6.92 CFP (W) 20 90.5828 mm² 13.09 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 6.3 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With
    3.3-V VCC)
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 6.3 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With
    3.3-V VCC)
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

The SN54LVCH245A octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVCH245A octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

The SN54LVCH245A octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVCH245A octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
filter 기타 범용 트랜시버 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
33개 모두 보기
유형 직함 날짜
* Data sheet SNx4LVCH245A Octal Bus Transceivers With Tri-State Outputs datasheet (Rev. Q) PDF | HTML 2018/09/19
* SMD SN54LVCH245A-SP SMD 5962-97543 2016/07/08
Application brief DLA Approved Optimizations for QML Products (Rev. B) PDF | HTML 2024/10/23
Selection guide TI Space Products (Rev. J) 2024/02/12
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023/08/31
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022/11/17
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 핀 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 20 Ultra Librarian
CFP (W) 20 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상