홈 로직 및 전압 변환 전압 변환기 및 레벨 시프터 방향 제어 전압 변환기
홈
로직 및 전압 변환
전압 변환기 및 레벨 시프터
방향 제어 전압 변환기

SN54SLC8T245-SEP

활성

방사능 내성, 8비트, 0.65V~3.3V, 방향 제어 레벨 트랜스레이터

지금 주문
데이터 시트

SN54SLC8T245-SEP

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family SLC Applications RGMII Bits (#) 8 High input voltage (min) (V) 0.4555 High input voltage (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 70 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Space Operating temperature range (°C) -55 to 125
Technology family SLC Applications RGMII Bits (#) 8 High input voltage (min) (V) 0.4555 High input voltage (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 70 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Space Operating temperature range (°C) -55 to 125
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4

  • VID V62/22604

  • Radiation tolerant:
    • Single event latch-up (SEL) immune up to 43 MeV-cm 2 /mg at 125°C
    • Total ionizing dose (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 20 krad(Si)
  • Qualified, fully configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
  • Operating temperature from –55°C to +125°C
  • Multiple direction-control pins allows simultaneous up and down translation
  • Up to 380 Mbps support when translating from 1.8 V to 3.3 V
  • V CC isolation feature that effectively isolates both buses in a power-down scenario
  • Partial power-down mode to limit backflow current in a power-down scenario
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 8000-V human-body model
    • 1000-V charged-device model

  • VID V62/22604

  • Radiation tolerant:
    • Single event latch-up (SEL) immune up to 43 MeV-cm 2 /mg at 125°C
    • Total ionizing dose (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 20 krad(Si)
  • Qualified, fully configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
  • Operating temperature from –55°C to +125°C
  • Multiple direction-control pins allows simultaneous up and down translation
  • Up to 380 Mbps support when translating from 1.8 V to 3.3 V
  • V CC isolation feature that effectively isolates both buses in a power-down scenario
  • Partial power-down mode to limit backflow current in a power-down scenario
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 8000-V human-body model
    • 1000-V charged-device model

The SN54SLC8T245-SEP device is an 8-bit non-inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, and 3.3 V).

The device operates by using two independent power-supply rails (V CCA and V CCB) that operate as low as 0.65 V. Data pins A1 through A8 are designed to track V CCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track V CCB, which accepts any supply voltage from 0.65 V to 3.6 V.

The SN54SLC8T245-SEP device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable ( OE) input is used to disable the outputs so the buses are effectively isolated.

The SN54SLC8T245-SEP device is designed so the control pins (DIR and OE) are referenced to V CCA.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The V CC isolation feature is designed so that if either V CC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state.

To put the level shifter I/Os in the high-impedance state during power up or power down, tie OE to V CCA through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

The SN54SLC8T245-SEP device is an 8-bit non-inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, and 3.3 V).

The device operates by using two independent power-supply rails (V CCA and V CCB) that operate as low as 0.65 V. Data pins A1 through A8 are designed to track V CCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track V CCB, which accepts any supply voltage from 0.65 V to 3.6 V.

The SN54SLC8T245-SEP device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable ( OE) input is used to disable the outputs so the buses are effectively isolated.

The SN54SLC8T245-SEP device is designed so the control pins (DIR and OE) are referenced to V CCA.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The V CC isolation feature is designed so that if either V CC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state.

To put the level shifter I/Os in the high-impedance state during power up or power down, tie OE to V CCA through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.
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기술 자료

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6개 모두 보기
유형 직함 날짜
* Data sheet SN54SLC8T245-SEP8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs datasheet (Rev. B) PDF | HTML 2023/12/05
* Radiation & reliability report SN54SLC8T245-SEP Production Flow and Reliability Report PDF | HTML 2022/10/20
* Radiation & reliability report SN54SLC8T245-SEP Single Event Effects Report PDF | HTML 2022/10/12
* Radiation & reliability report SN54SLC8T245-SEP Total Ionizing Dose (TID) PDF | HTML 2022/10/03
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024/05/14
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024/04/30

설계 및 개발

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평가 보드

AVCLVCDIRCNTRL-EVM — AVC 및 LVC를 지원하는 방향 제어 양방향 변환 디바이스를 위한 일반 EVM

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

사용 설명서: PDF
TI.com에서 구매 불가
평가 보드

ALPHA-3P-ADM-VA600-SPACE-AMD — AMD Versal 코어 XQRVC1902 ACAP 및 TI 방사선 내성 제품을 사용하는 Alpha Data ADM-VA600 키트

AMD-Xilinx® Versal AI Core XQRVC1902 적응형 SoC/FPGA를 강조하는 6U VPX 폼 팩터입니다. ADM-VA600은 FMC+ 커넥터 1개, DDR4 DRAM 및 시스템 모니터링 기능을 갖춘 모듈식 보드 설계입니다. 대부분의 구성 요소는 방사능 내성 전원 관리, 인터페이스, 클로킹 및 임베디드 프로세싱(-SEP) 장치입니다.

발송: Alpha Data Parallel Systems Ltd.
파트너 사이트 방문
평가 보드

ALPHA-3P-ADM-VA601-SPACE-AMD — AMD Versal 코어 XQRVC1902 ACAP 및 TI 방사선 내성 제품을 사용하는 Alpha Data ADM-VA601 키트

AMD-Xilinx®® Versal AI Core XQRVC1902 적응형 SoC/FPGA를 강조하는 6U VPX 폼 팩터입니다. ADM-VA600은 FMC+ 커넥터 1개, DDR4 DRAM 및 시스템 모니터링 기능을 갖춘 모듈식 보드 설계입니다. 대부분의 구성 요소는 방사능 내성 전원 관리, 인터페이스, 클로킹 및 임베디드 프로세싱(-SEP) 장치입니다.

발송: Alpha Data Parallel Systems Ltd.
파트너 사이트 방문
시뮬레이션 모델

SN54SLC8T245-SEP IBIS Model (Rev. B)

SCEM795B.ZIP (82 KB) - IBIS Model
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TSSOP (PW) 24 Ultra Librarian
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  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
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  • 지속적인 신뢰성 모니터링
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