제품 상세 정보

Configuration 1:1 SPST Number of channels 8 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 5 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
Configuration 1:1 SPST Number of channels 8 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 5 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SSOP (DBQ) 20 51.9 mm² 8.65 x 6 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4
  • Standard ’245-Type Pinout
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on All Data I/O Ports
    • 5-V Input Down to 3.3-V Output Level Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V VCC
  • 5-V-Tolerant I/Os With Device Powered Up or Powered Down
  • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typical)
  • Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 40 µA Maximum)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or
    5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Ideal for Low-Power Portable Equipment
  • Standard ’245-Type Pinout
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on All Data I/O Ports
    • 5-V Input Down to 3.3-V Output Level Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V VCC
  • 5-V-Tolerant I/Os With Device Powered Up or Powered Down
  • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typical)
  • Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 40 µA Maximum)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or
    5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Ideal for Low-Power Portable Equipment

The SN74CB3T3245 device is a high-speed TTL-compatible 8-bit FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC.

The SN74CB3T3245 device is a high-speed TTL-compatible 8-bit FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC.

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기술 자료

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14개 모두 보기
유형 직함 날짜
* Data sheet SN74CB3T3245 8-Bit FET Bus Switch 2.5-V and 3.3-V Low-Voltage With 5-V-Tolerant Level Shifter datasheet (Rev. C) PDF | HTML 2018/05/31
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/06/02
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/01
Application note CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. C) PDF | HTML 2021/11/19
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021/01/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
More literature Digital Bus Switch Selection Guide (Rev. A) 2004/11/10
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Bus FET Switch Solutions for Live Insertion Applications 2003/02/07

설계 및 개발

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인터페이스 어댑터

LEADED-ADAPTER1 — TI의 5, 8, 10, 16 및 24핀 리드 패키지의 빠른 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

HSPICE Model for SN74CB3T3245

SCDJ028.ZIP (99 KB) - HSpice Model
시뮬레이션 모델

SN74CB3T3245 IBIS Model

SCDM055.ZIP (26 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
SOIC (DW) 20 Ultra Librarian
SSOP (DBQ) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

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