인터페이스 기타 인터페이스

TLK10081

활성

10Gbps 1~8채널 다중 속도 이중화 링크 애그리게이터

제품 상세 정보

Protocols Catalog Device type Aggregator Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Device type Aggregator Rating Catalog Operating temperature range (°C) -40 to 85
FCBGA (CTR) 144 169 mm² 13 x 13
  • Automatic Digital Multiplexing/De-Multiplexing of 1 to 8
    Independent Lower Speed Gigabit Serial Lines into a Single
    Higher Speed Gigabit Serial Line with Extensive Media
    Transmission Capabilities.
  • 1∼8 × (0.25 to 1.25 Gbps) to 1 x (2 to 10 Gbps) Multiplexing
  • 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
  • Dynamic Port Aggregation Supported
  • Programmable High Speed Redundant Switching
  • Wide Data Rate Range for Multiple Application Support
  • Transmit De-Emphasis and Adaptive Receiver Equalization on
    Both Low Speed and High Speed Sides
  • MDIO Clause 22 control interface
  • 8B/10B ENDEC Coding Support
  • Raw (Unencoded) Data Support
  • Core Supply 1V; I/O: 1.5V/1.8V
  • Superior Signal Integrity Performance
  • Low Power Operation: < 800 mW per channel (typ)
  • Rate Matching Support (For compatible data protocols like GE PCS)
  • Full Non-Blocking Receiver Crosspoint Mapping Capability
  • Flexible Clocking
  • Multi Drive Capability (SFP+, backplane, cable)
  • Support for Programmable High Speed Lane Alignment Characters
  • Support for Programmable HS/LS 10-Bit Alignment Characters
  • Wide Range of Built-in Test Patterns
  • 144-pin, 13mmx13mm FCBGA Package
  • Automatic Digital Multiplexing/De-Multiplexing of 1 to 8
    Independent Lower Speed Gigabit Serial Lines into a Single
    Higher Speed Gigabit Serial Line with Extensive Media
    Transmission Capabilities.
  • 1∼8 × (0.25 to 1.25 Gbps) to 1 x (2 to 10 Gbps) Multiplexing
  • 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
  • Dynamic Port Aggregation Supported
  • Programmable High Speed Redundant Switching
  • Wide Data Rate Range for Multiple Application Support
  • Transmit De-Emphasis and Adaptive Receiver Equalization on
    Both Low Speed and High Speed Sides
  • MDIO Clause 22 control interface
  • 8B/10B ENDEC Coding Support
  • Raw (Unencoded) Data Support
  • Core Supply 1V; I/O: 1.5V/1.8V
  • Superior Signal Integrity Performance
  • Low Power Operation: < 800 mW per channel (typ)
  • Rate Matching Support (For compatible data protocols like GE PCS)
  • Full Non-Blocking Receiver Crosspoint Mapping Capability
  • Flexible Clocking
  • Multi Drive Capability (SFP+, backplane, cable)
  • Support for Programmable High Speed Lane Alignment Characters
  • Support for Programmable HS/LS 10-Bit Alignment Characters
  • Wide Range of Built-in Test Patterns
  • 144-pin, 13mmx13mm FCBGA Package

The TLK10081 is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.

The TLK10081 has a low-speed interface which can accommodate one to eight bidirectional serial links running at rates from 250 Mbps to 1.25 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces can operate at rates from 1 Gbps to 10 Gbps. The high speed interface is designed to run at 8 x the low speed serial rate regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so TX may operate in 8:1 mode while RX operates in 1:1 mode. This independence is restricted to using the same low speed line rate. For example, the TX can operate at 8 × 1.25 Gbps while RX operates at 1 × 1.25 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.

The TLK10081 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10081 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.

The TLK10081 is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.

The TLK10081 has a low-speed interface which can accommodate one to eight bidirectional serial links running at rates from 250 Mbps to 1.25 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces can operate at rates from 1 Gbps to 10 Gbps. The high speed interface is designed to run at 8 x the low speed serial rate regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so TX may operate in 8:1 mode while RX operates in 1:1 mode. This independence is restricted to using the same low speed line rate. For example, the TX can operate at 8 × 1.25 Gbps while RX operates at 1 × 1.25 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.

The TLK10081 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10081 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능
TLK10002 활성 듀얼 채널 10Gbps 다중 속도 트랜시버 Dual Channel 10Gbps Serdes with support for CPRI and OBSAI data rates
TLK10022 활성 10Gbps 듀얼 채널 다중 속도 범용 링크 애그리게이터 Duall Channel 10Gbps 4:1/1:4 Aggregator
TLK10232 활성 크로스포인트 스위치를 지원하는 듀얼 채널 XAUI-to-10GBASE-KR 백플레인 트랜시버 10GbE Compliant Dual Channel Phy

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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5개 모두 보기
유형 직함 날짜
* Data sheet 10Gbps 1-8 Channel Multi-Rate Serial Link Aggregator datasheet 2013/11/08
Application note Video Aggregation HD-SDI Interface Application Sheet 2014/10/01
Application note Link Aggregation Interface Application Sheet 2014/01/10
EVM User's guide TLK10022 and TLK10081 EVM User's Guide 2013/11/08
User guide TLK10022 and TLK10081 Multi-Rate Lane Aggregator EVM GUI User's Guide 2013/11/08

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 모듈(EVM)용 GUI

SLLC440 TLK10022/81 EVM GUI Software

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
기타 인터페이스
TLK10022 10Gbps 듀얼 채널 다중 속도 범용 링크 애그리게이터 TLK10081 10Gbps 1~8채널 다중 속도 이중화 링크 애그리게이터
시뮬레이션 모델

TLK10081 Hspice Model

SLLM233.ZIP (9164 KB) - HSpice Model
시뮬레이션 모델

TLK10081 IBIS Model

SLLM234.ZIP (60 KB) - IBIS Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
레퍼런스 디자인

TIDA-00269 — 기가비트 이더넷 링크 애그리게이터 레퍼런스 디자인

The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
Test report: PDF
회로도: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
FCBGA (CTR) 144 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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