TMS320DM365

Name: TMS320DM365
Brand: TI
SKU: TMS320DM365
Price: 10.155 USD

활성

DaVinci 디지털 미디어 프로세서

지금 주문

데이터 시트

document-pdfAcrobat TMS320DM365 Digital Media System-on-Chip datasheet (Rev. E) (영어)

정오표

document-pdfAcrobat
TMS320DM365 Digital Media System-on-Chip Silicon Errata (Silicon Revs 1.1 & 1.2) (Rev. E) (영어)

TMS320DM365

활성

데이터 시트

지금 주문

제품 상세 정보

DSP type

Operating system

Linux

Ethernet MAC

10/100

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSP type

Operating system

Linux

Ethernet MAC

10/100

Rating

Catalog

Operating temperature range (°C)

-40 to 85

NFBGA (ZCE)

338

169 mm² 13 x 13

Highlights
- High-Performance Digital Media System-on-Chip (DMSoC)
- Up to 300-MHz ARM926EJ-S Clock Rate
- Two Video Image Co-processors (HDVICP, MJCP) Engines
- Supports a Range of Encode, Decode, and Video Quality Operations
- Video Processing Subsystem
  - HW Face Detect Engine
  - Resize Engine from 1/16x to 8x
  - 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz
  - 4:2:2 (8-/16-bit) Interface
  - 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
  - 3 DACs for HD Analog Video Output
  - Hardware On-Screen Display (OSD)
- Capable of 720p 30fps H.264 video processing
  Note: 216-MHz is only capable of D1 processing
- Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan
- 8 Different Boot Modes and Configurable Power-Saving Modes
- Pin-to-pin and software compatible with DM368
- Extended temperature (-40°C - 85°C) available for 300-Mhz device
- 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core
- 338-Pin Ball Grid Array at 65nm Process Technology
High-Performance Digital Media System-on-Chip (DMSoC)
- 216-, 270-, 300-MHz ARM926EJ-S Clock Rate
- Fully Software-Compatible With ARM9™
ARM926EJ-S™ Core
- Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- EmbeddedICE-RT Logic for Real-Time Debug
ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 16K-Byte ROM
- Little Endian
Two Video Image Co-processors (HDVICP, MJCP) Engines
- Support a Range of Encode and Decode Operations
- H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
Video Processing Subsystem
- Front End Provides:
  - HW Face Detect Engine
  - Hardware IPIPE for Real-Time Image Processing
    - Resize Engine
      - Resize Images From 1/16× to 8×
      - Separate Horizontal/Vertical Control
      - Two Simultaneous Output Paths
  - IPIPE Interface (IPIPEIF)
  - Image Sensor Interface (ISIF) and CMOS Imager Interface
  - 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
  - Glueless Interface to Common Video Decoders
  - BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit Module
  - Histogram Module
  - Lens distortion correction module (LDC)
  - Hardware 3A statistics collection module (H3A)
- Back End Provides:
  - Hardware On-Screen Display (OSD)
  - Composite NTSC/PAL video encoder output
  - 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
  - 3 DACs for HD Analog Video Output
  - LCD Controller
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
Analog-to-Digital Convertor (ADC)
Power Management and Real Time Clock Subsystem (PRTCSS)
- Real Time Clock
16-Bit Host-Port Interface (HPI)
10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media
- IEEE 802.3 Compliant
- Supports Media Independent Interface (MII)
- Management Data I/O (MDIO) Module
Key Scan
Voice Codec
External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
- Asynchronous16-/8-bit Wide EMIF (AEMIF)
  - Flash Memory Interfaces
    - NAND (8-/16-bit Wide Data)
    - 16 MB NOR Flash, SRAM
    - OneNAND(16-bit Wide Data)
Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
- SmartMedia/xD
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
USB port with Integrated 2.0 High-Speed PHY that Supports
- USB 2.0 High-Speed Device
- USB 2.0 High-Speed Host (mini-host, supporting one external device)
- USB On The Go (HS-USB OTG)
Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Two UARTs (One fast UART with RTS and CTS Flow Control)
Five Serial Port Interfaces (SPI) each with two Chip-Selects
One Master/Slave Inter-Integrated Circuit (I²C) Bus™
One Multi-Channel Buffered Serial Port (McBSP)
- I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
- Direct Interface to T1/E1 Framers
- Time Division Multiplexed Mode (TDM)
- 128 Channel Mode
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
Boot Modes
- On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
- AEMIF (NOR and OneNAND)
Configurable Power-Saving Modes
Crystal or External Clock Input (typically 19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
- IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
- ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
- Device Revision ID Readable by ARM
338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
65nm Process Technology
3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal
Community Reesources
- TI E2E Community
- TI Embedded Processors Wiki

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Windows is a trademark of Microsoft.

All other trademarks are the property of their respective owners.

Highlights
- High-Performance Digital Media System-on-Chip (DMSoC)
- Up to 300-MHz ARM926EJ-S Clock Rate
- Two Video Image Co-processors (HDVICP, MJCP) Engines
- Supports a Range of Encode, Decode, and Video Quality Operations
- Video Processing Subsystem
  - HW Face Detect Engine
  - Resize Engine from 1/16x to 8x
  - 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz
  - 4:2:2 (8-/16-bit) Interface
  - 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
  - 3 DACs for HD Analog Video Output
  - Hardware On-Screen Display (OSD)
- Capable of 720p 30fps H.264 video processing
  Note: 216-MHz is only capable of D1 processing
- Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan
- 8 Different Boot Modes and Configurable Power-Saving Modes
- Pin-to-pin and software compatible with DM368
- Extended temperature (-40°C - 85°C) available for 300-Mhz device
- 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core
- 338-Pin Ball Grid Array at 65nm Process Technology
High-Performance Digital Media System-on-Chip (DMSoC)
- 216-, 270-, 300-MHz ARM926EJ-S Clock Rate
- Fully Software-Compatible With ARM9™
ARM926EJ-S™ Core
- Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- EmbeddedICE-RT Logic for Real-Time Debug
ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 16K-Byte ROM
- Little Endian
Two Video Image Co-processors (HDVICP, MJCP) Engines
- Support a Range of Encode and Decode Operations
- H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
Video Processing Subsystem
- Front End Provides:
  - HW Face Detect Engine
  - Hardware IPIPE for Real-Time Image Processing
    - Resize Engine
      - Resize Images From 1/16× to 8×
      - Separate Horizontal/Vertical Control
      - Two Simultaneous Output Paths
  - IPIPE Interface (IPIPEIF)
  - Image Sensor Interface (ISIF) and CMOS Imager Interface
  - 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
  - Glueless Interface to Common Video Decoders
  - BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit Module
  - Histogram Module
  - Lens distortion correction module (LDC)
  - Hardware 3A statistics collection module (H3A)
- Back End Provides:
  - Hardware On-Screen Display (OSD)
  - Composite NTSC/PAL video encoder output
  - 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
  - 3 DACs for HD Analog Video Output
  - LCD Controller
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
Analog-to-Digital Convertor (ADC)
Power Management and Real Time Clock Subsystem (PRTCSS)
- Real Time Clock
16-Bit Host-Port Interface (HPI)
10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media
- IEEE 802.3 Compliant
- Supports Media Independent Interface (MII)
- Management Data I/O (MDIO) Module
Key Scan
Voice Codec
External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
- Asynchronous16-/8-bit Wide EMIF (AEMIF)
  - Flash Memory Interfaces
    - NAND (8-/16-bit Wide Data)
    - 16 MB NOR Flash, SRAM
    - OneNAND(16-bit Wide Data)
Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
- SmartMedia/xD
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
USB port with Integrated 2.0 High-Speed PHY that Supports
- USB 2.0 High-Speed Device
- USB 2.0 High-Speed Host (mini-host, supporting one external device)
- USB On The Go (HS-USB OTG)
Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Two UARTs (One fast UART with RTS and CTS Flow Control)
Five Serial Port Interfaces (SPI) each with two Chip-Selects
One Master/Slave Inter-Integrated Circuit (I²C) Bus™
One Multi-Channel Buffered Serial Port (McBSP)
- I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
- Direct Interface to T1/E1 Framers
- Time Division Multiplexed Mode (TDM)
- 128 Channel Mode
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
Boot Modes
- On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
- AEMIF (NOR and OneNAND)
Configurable Power-Saving Modes
Crystal or External Clock Input (typically 19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
- IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
- ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
- Device Revision ID Readable by ARM
338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
65nm Process Technology
3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal
Community Reesources
- TI E2E Community
- TI Embedded Processors Wiki

Developers can now deliver pixel-perfect images at up to 720p H.264 at 30fps in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas Instruments Incorporated (TI). With multi-format HD video, the DM365 also features a suite of peripherals saving developers on system costs.

This ARM9-based DM365 device offers speeds up to 300 MHz and supports production-qualified H.264, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs are driven from video accelerators offloading compression needs from the ARM core so that developers can utilize the most performance from the ARM for their application. Video surveillance designers achieve greater compression efficiency providing more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can ensure interoperability as well as product scalability by taking advantage of the full suite of codecs supported on the DM365.

Along with multi-format HD video, the DM365 enables seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM365 also offers a high level of integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI), Analog to Digital Converter, and many more features saving developers on overall system costs as well as real estate on their circuit boards allowing for a slimmer, sleeker design.

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47개 모두 보기

	유형	직함		날짜
*	Data sheet	TMS320DM365 Digital Media System-on-Chip datasheet (Rev. E)		2011/07/01
*	Errata	TMS320DM365 Digital Media System-on-Chip Silicon Errata (Silicon Revs 1.1 & 1.2) (Rev. E)		2011/07/11
	Application note	High-Speed Interface Layout Guidelines (Rev. J)	PDF \| HTML	2023/02/24
	User guide	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		2020/06/01
	User guide	TMS320DM36x DaVinci™ Video Processing Front End (VPFE) User's Guide (Rev. C)		2016/06/30
	Application note	Powering the TMS320DM365 using the TPS650061		2012/05/10
	User guide	TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem User's Guide (Rev. B)		2011/08/03
	Application note	Migrating From TMS320DM35x to TMS320DM36x Devices (Rev. A)		2011/06/02
	User guide	TMS320DM36x DMSoC General-Purpose Input/Output User's Guide (Rev. C)		2011/01/19
	User guide	TMS320DM36x DMSoC Ethernet Media Access Controller (EMAC) User's Guide (Rev. B)		2010/12/23
	User guide	TMS320DM36x DMSoC Video Processing Front End User's Guide (Rev. C)		2010/11/12
	User guide	TMS320DM36x DMSoC Video Processing Back End User's Guide (Rev. C)		2010/08/26
	User guide	TMS320DM36x DMSoC Voice Codec User's Guide (Rev. B)		2010/07/30
	User guide	TMS320DM36x DMSoC Face Detection User's Guide (Rev. A)		2010/07/21
	Application note	Application Parameter Settings for TMS320DM365 H.264 Encoder		2010/04/29
	User guide	TMS320DM36x DMSoC Asynchronous External Memory Interface User's Guide (Rev. C)		2010/04/23
	User guide	TMS320DM36x DMSoC Multimedia Card/Secure Digital Card Controller User's Guide (Rev. B)		2010/04/23
	Application note	Migrating from TMS320DM365 to TMS320DM368		2010/04/11
	More literature	TMS320DM3x DaVinci Video Processors		2010/04/11
	User guide	TMS320DM36x DMSoC Key Scan User's Guide (Rev. A)		2010/03/01
	User guide	TMS320DM36x DMSoC Serial Peripheral Interface User's Guide (Rev. B)		2010/03/01
	Application note	Smart Codec Features in TMS320DM365		2009/12/09
	Application note	TMS320DM365 Preview of Codec Porting on Linux		2009/12/04
	Application note	Understanding H.264 Decoder Buffer Mechanism for TMS320DM365		2009/12/04
	Application note	High-Efficiency Power Solution Using DC/DC Converter for the DM365 (Rev. A)		2009/09/11
	Application note	Simple Power Solution Using LDOs for the DM365 (Rev. A)		2009/09/11
	Application note	High Integration, High Efficiency Power Solution using DCDC Converters for DM365 (Rev. A)		2009/09/11
	Application note	TMS320DM36x Power Consumption Summary		2009/09/10
	User guide	TMS320DM36x DMSoC Universal Host Port Interface User's Guide (Rev. A)		2009/08/09
	User guide	TMS320DM36x DMSoC ARM Subsystem Reference Guide (Rev. A)		2009/08/07
	User guide	TMS320DM36x DMSoC Inter-Integrated Circuit User's Guide (Rev. A)		2009/08/07
	User guide	TMS320DM36x DMSoC Multichannel Buffered Serial Port User's Guide (Rev. A)		2009/08/07
	User guide	TMS320DM36x DMSoC Universal Serial Bus User's Guide (Rev. A)		2009/08/07
	Application note	High Integration, High Efficiency Power Solution using DCDC Converters for DM365		2009/08/04
	Application note	High-Vin, High-Efficiency Power Solution Using DC/DC Converter for the DM365		2009/08/04
	Application note	Simple Power Solution Using LDOs for the DM365		2009/08/04
	Application note	TMS320DM36x SoC Architecture and Throughput		2009/07/29
	Application note	LSP 2.10 DaVinci Linux Drivers (Rev. A)		2009/07/08
	More literature	Complimentary Analog Devices for DM365 Digital Media Processor		2009/03/03
	User guide	TMS320DM36x DMSoC Analog to Digital Converter User's Guide		2009/03/03
	User guide	TMS320DM36x DMSoC DDR2/mDDR Memory Controller User's Guide		2009/03/03
	User guide	TMS320DM36x DMSoC Enhanced Direct Memory Access Controller User's Guide		2009/03/03
	User guide	TMS320DM36x DMSoC Pulse-Width Modulator User's Guide		2009/03/03
	User guide	TMS320DM36x DMSoC Real Time Out User's Guide		2009/03/03
	User guide	TMS320DM36x DMSoC Timer/Watchdog Timer User's Guide		2009/03/03
	User guide	TMS320DM36x DMSoC Universal Asynchronous Receiver/Transmitter User's Guide		2009/03/03
	Application note	Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A)		2008/07/17

설계 및 개발

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평가 보드

TMDXEVM368 — TMS320DM36x 평가 모듈

The TMS320DM36x Digital Video Evaluation Module (DVEVM) enables developers to start immediate evaluation of TI’s Digital Media (DMx) processors and begin building digital video applications such as IP security cameras, action cameras, drones, wearables, digital signage, video doorbells, and (...)

사용 설명서: PDF

TI.com에서 구매 불가

디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

TI.com에서 구매 불가

디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

TI.com에서 구매 불가

디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

TI.com에서 구매 불가

소프트웨어 개발 키트(SDK)

LINUXDVSDK-DM36X — DM365, DM368 디지털 미디어 프로세서용 DVSDK(Linux 디지털 비디오 소프트웨어 개발 키트)

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci™ system integrators to quickly develop Linux-based multimedia applications that can be easily ported across different devices in the DaVinci platform. Each DVSDK combines a pre-tested set of operating system, application (...)

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소프트웨어 코덱

DM365CODECS — Codecs for DM36x (DM365, DM368) - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

지원되는 제품 및 하드웨어

제품

DSP(디지털 신호 프로세서)

TMS320DM365 — DaVinci 디지털 미디어 프로세서

TMS320DM368 — DaVinci 디지털 미디어 프로세서

다운로드 옵션

시뮬레이션 모델

DM365 ZCE BSDL Model

SPRM363.ZIP (9 KB) - BSDL Model

다운로드

시뮬레이션 모델

DM365 ZCE IBIS Model (Rev. C)

SPRM354C.ZIP (502 KB) - IBIS Model

다운로드

패키지	핀	CAD 기호, 풋프린트 및 3D 모델
NFBGA (ZCE)	338	Ultra Librarian

TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:

RoHS
REACH
디바이스 마킹
납 마감/볼 재질
MSL 등급/피크 리플로우
MTBF/FIT 예측
물질 성분
인증 요약
지속적인 신뢰성 모니터링

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지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요.

비디오 시리즈

모든 비디오 보기

TMS320DM365

DaVinci 디지털 미디어 프로세서

TMS320DM365

제품 상세 정보

타사를 통해 지원

기술 자료

설계 및 개발

TMDXEVM368 — TMS320DM36x 평가 모듈

TMDSEMU200-U — XDS200 USB 디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

LINUXDVSDK-DM36X — DM365, DM368 디지털 미디어 프로세서용 DVSDK(Linux 디지털 비디오 소프트웨어 개발 키트)

DM365CODECS — Codecs for DM36x (DM365, DM368) - Software and Documentation

지원되는 제품 및 하드웨어

제품

DSP(디지털 신호 프로세서)

DM365 ZCE BSDL Model

DM365 ZCE IBIS Model (Rev. C)

주문 및 품질

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

비디오 시리즈

동영상

옵션 다운로드

DM365CODECS — Codecs for DM36x (DM365, DM368) - Software and Documentation

DSP(디지털 신호 프로세서)

문서

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