제품 상세 정보

Protocols DDR3 Configuration 2:1 SPDT Number of channels 12 Bandwidth (MHz) 1675 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 3 Ron (typ) (mΩ) 8000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Supply current (typ) (µA) 300 ESD HBM (typ) (kV) 2 Operating temperature range (°C) -40 to 85 Crosstalk (dB) -71 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5.6 CON (typ) (pF) 2 Off isolation (typ) (dB) -42 OFF-state leakage current (max) (µA) 1 Propagation delay time (µs) 0.00004 Ron (max) (mΩ) 12000 Ron channel match (max) (Ω) 1 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 5 Turnon time (enable) (max) (ns) 7 VIH (min) (V) 2 VIL (max) (V) 0.8
Protocols DDR3 Configuration 2:1 SPDT Number of channels 12 Bandwidth (MHz) 1675 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 3 Ron (typ) (mΩ) 8000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Supply current (typ) (µA) 300 ESD HBM (typ) (kV) 2 Operating temperature range (°C) -40 to 85 Crosstalk (dB) -71 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5.6 CON (typ) (pF) 2 Off isolation (typ) (dB) -42 OFF-state leakage current (max) (µA) 1 Propagation delay time (µs) 0.00004 Ron (max) (mΩ) 12000 Ron channel match (max) (Ω) 1 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 5 Turnon time (enable) (max) (ns) 7 VIH (min) (V) 2 VIL (max) (V) 0.8
WQFN (RUA) 42 31.5 mm² 9 x 3.5
  • Compatible with DDR3 SDRAM Standard (JESD79-3D)
  • Wide Bandwidth of 1.675 GHz
  • Low Propagation Delay (tpd = 40 ps Typ)
  • Low Bit-to-Bit Skew (tsk(o) = 6 ps Typ)
  • Low and Flat ON-State Resistance
    (rON = 8 Ω Typ)
  • Low Input/Output Capacitance
    (CON = 5.6 pF Typ)
  • Low Crosstalk (XTALK = –43 dB,
    Typ at 250 MHz)
  • VCC Operating Range from 3 V to 3.6 V
  • Rail-to-Rail Switching on Data I/O Ports
    (0 to VCC)
  • Separate Switch Control Logic for Upper and Lower 6-Channels
  • Dedicated Enable Logic Supports Hi-Z Mode
  • IOFF Protection Prevents Current Leakage in Powered Down State (VCC = 0 V)
  • ESD Performance Tested Per JESD22
    • 2000 V Human Body Model
      (A114B, Class II)
    • 1000 V Charged Device Model (C101)
  • 42-pin RUA Package (9 × 3.5 mm, 0.5 mm Pitch)
  • Compatible with DDR3 SDRAM Standard (JESD79-3D)
  • Wide Bandwidth of 1.675 GHz
  • Low Propagation Delay (tpd = 40 ps Typ)
  • Low Bit-to-Bit Skew (tsk(o) = 6 ps Typ)
  • Low and Flat ON-State Resistance
    (rON = 8 Ω Typ)
  • Low Input/Output Capacitance
    (CON = 5.6 pF Typ)
  • Low Crosstalk (XTALK = –43 dB,
    Typ at 250 MHz)
  • VCC Operating Range from 3 V to 3.6 V
  • Rail-to-Rail Switching on Data I/O Ports
    (0 to VCC)
  • Separate Switch Control Logic for Upper and Lower 6-Channels
  • Dedicated Enable Logic Supports Hi-Z Mode
  • IOFF Protection Prevents Current Leakage in Powered Down State (VCC = 0 V)
  • ESD Performance Tested Per JESD22
    • 2000 V Human Body Model
      (A114B, Class II)
    • 1000 V Charged Device Model (C101)
  • 42-pin RUA Package (9 × 3.5 mm, 0.5 mm Pitch)

The TS3DDR3812 is a 12-channel, 1:2 multiplexer/demultiplexer switch designed for DDR3 applications. It operates from a 3 to 3.6 V supply and offers low and flat ON-state resistance as well as low I/O capacitance which allow it to achieve a typical bandwidth of 1.675 GHz.

Channels A0 through A11 are divided into two banks of six bits and are independently controlled via two digital inputs called SEL1 and SEL2. These select inputs control the switch position of each 6-bit DDR3 source and allow them to be routed to one of two end-points. Alternatively, the switch can be used to connect a single endpoint to one of two 6-bit DDR3 sources. For switching 12-bit DDR3 sources, simply connect SEL1 and SEL2 together externally and control all 12 channels with a single GPIO input. An EN input allows the entire chip to be placed into a high-impedance (Hi-Z) state while not in use.

These characteristics make the TS3DDR3812 an excellent choice for use in memory, analog/digital video, LAN, and other high-speed signal switching applications.

The TS3DDR3812 is a 12-channel, 1:2 multiplexer/demultiplexer switch designed for DDR3 applications. It operates from a 3 to 3.6 V supply and offers low and flat ON-state resistance as well as low I/O capacitance which allow it to achieve a typical bandwidth of 1.675 GHz.

Channels A0 through A11 are divided into two banks of six bits and are independently controlled via two digital inputs called SEL1 and SEL2. These select inputs control the switch position of each 6-bit DDR3 source and allow them to be routed to one of two end-points. Alternatively, the switch can be used to connect a single endpoint to one of two 6-bit DDR3 sources. For switching 12-bit DDR3 sources, simply connect SEL1 and SEL2 together externally and control all 12 channels with a single GPIO input. An EN input allows the entire chip to be placed into a high-impedance (Hi-Z) state while not in use.

These characteristics make the TS3DDR3812 an excellent choice for use in memory, analog/digital video, LAN, and other high-speed signal switching applications.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치보다 업그레이드된 기능을 지원하는 드롭인 대체품
TS3DDR4000 활성 3.3V, 2:1(SPDT), 12채널 DDR2, DDR3 및 DDR4 스위치 Flipped logic polarity (normally closed)

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
3개 모두 보기
유형 직함 날짜
* Data sheet 12-CHANNEL, 1:2 MUX/DEMUX SWITCH FOR DDR3 APPLICATIONS datasheet (Rev. B) 2013/06/03
Application note Preventing Excess Power Consumption on Analog Switches 2008/07/03
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08

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평가 보드

LP-AM263 — AM263x 런치패드

LP-AM263 은 AM263x 시리즈의 Sitara™ 고성능 마이크로컨트롤러(MCU)용 비용 최적화된 개발 보드입니다. 이 보드는 다음 애플리케이션을 개발할 수 있는 표준화되고 사용하기 쉬운 플랫폼을 제공하므로 초기 평가 및 프로토타이핑에 이상적입니다.

LP-AM263에는 Sitara AM2634 프로세서와 추가 부품이 포함되어 있어, 사용자가 산업용 이더넷(IE), 표준 이더넷, 고속 직렬 인터페이스(FSI) 등을 포함한 다양한 디바이스 인터페이스를 사용하여 프로토타입을 쉽게 제작할 수 있습니다. AM2634는 (...)

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시뮬레이션 모델

TS3DDR3812 HSpice Model

SCDM134.ZIP (113 KB) - HSpice Model
시뮬레이션 모델

TS3DDR3812 IBIS

SCDM135.ZIP (24 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
WQFN (RUA) 42 Ultra Librarian

주문 및 품질

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  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
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  • 팹 위치
  • 조립 위치

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