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SN74AHCT1G126

ACTIVE

Single 4.5-V to 5.5-V buffer with TTL-compatible CMOS inputs and 3-state outputs

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Data sheet

SN74AHCT1G126

ACTIVE
Data sheet Order now

Product details

Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 8 Supply current (max) (µA) 10 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 8 Supply current (max) (µA) 10 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Operating range of 4.5V to 5.5V
  • Max tpd of 6ns at 5V
  • Low power consumption, 10µA max ICC
  • ±8mA output drive at 5V
  • Inputs are TTL-voltage compatible
  • Latch-up performance exceeds 250mA per JESD 17
  • Operating range of 4.5V to 5.5V
  • Max tpd of 6ns at 5V
  • Low power consumption, 10µA max ICC
  • ±8mA output drive at 5V
  • Inputs are TTL-voltage compatible
  • Latch-up performance exceeds 250mA per JESD 17

The SN74AHCT1G126 device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.

The SN74AHCT1G126 device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.
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SN74AHCT1G125 ACTIVE Single 4.5-V to 5.5-V buffer with TTL-compatible CMOS inputs and 3-state outputs Voltage range (4.5V to 5.5V), average drive strength (8mA), average propagation delay (9ns)

Technical documentation

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Type Title Date
* Data sheet SN74AHCT1G126 Single Bus Buffer Gate With 3-State Output datasheet (Rev. L) PDF | HTML 19 Mar 2024
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

HSPICE Model for SN74AHCT1G126

SCLJ013.ZIP (85 KB) - HSpice Model
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Simulation model

SN74AHCT1G126 Behavioral SPICE Model

SCLM244.ZIP (7 KB) - PSpice Model
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Simulation model

SN74AHCT1G126 IBIS Model

SCLM019.ZIP (7 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOT-23 (DBV) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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