TPS3813

ACTIVE

voltage supervisor (reset IC) with programmable window watchdog

Product details

Number of supplies monitored 1 Threshold voltage 1 (typ) (V) 2.25, 2.64, 2.93, 4.55 Features Undervoltage monitor only, Watchdog timer, Window watchdog Reset threshold accuracy (%) 2.4 Iq (typ) (mA) 0.009 Output driver type/reset output Active-low, Open-drain Time delay (ms) 25 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Rating Catalog Watchdog timer WDI (s) Programmable Operating temperature range (°C) -40 to 85
Number of supplies monitored 1 Threshold voltage 1 (typ) (V) 2.25, 2.64, 2.93, 4.55 Features Undervoltage monitor only, Watchdog timer, Window watchdog Reset threshold accuracy (%) 2.4 Iq (typ) (mA) 0.009 Output driver type/reset output Active-low, Open-drain Time delay (ms) 25 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Rating Catalog Watchdog timer WDI (s) Programmable Operating temperature range (°C) -40 to 85
SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8
  • Window-watchdog with programmable delay and window ratio
  • 6-Pin SOT-23 package
  • Supply current of 9µA (typical)
  • Power-on reset generator with a fixed delay time of 25ms
  • Precision supply voltage monitor (VIT):2.5V, 3V, 3.3V, and 5V
  • Open-drain reset output
  • Temperature range:  –40°C to 85°C
  • Window-watchdog with programmable delay and window ratio
  • 6-Pin SOT-23 package
  • Supply current of 9µA (typical)
  • Power-on reset generator with a fixed delay time of 25ms
  • Precision supply voltage monitor (VIT):2.5V, 3V, 3.3V, and 5V
  • Open-drain reset output
  • Temperature range:  –40°C to 85°C

The TPS3813xxx family of supervisory circuits provide circuit initialization and timing supervision, primarily for DSPs and processor-based systems.

During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1V. Thereafter, the supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td = 25ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider.

For safety critical applications the TPS3813xxx family incorporates a so-called window-watchdog with programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting WDR to GND or VDD. The supervised processor now needs to trigger the TPS3813xxx within this window not to assert a RESET.

The product spectrum is designed for supply voltages of 2.5V, 3V, 3.3V, and 5V. The circuits are available in a 6-pin SOT-23 package.

The TPS3813xxx devices are characterized for operation over a temperature range of –40°C to 85°C.

The TPS3813xxx family of supervisory circuits provide circuit initialization and timing supervision, primarily for DSPs and processor-based systems.

During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1V. Thereafter, the supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td = 25ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider.

For safety critical applications the TPS3813xxx family incorporates a so-called window-watchdog with programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting WDR to GND or VDD. The supervised processor now needs to trigger the TPS3813xxx within this window not to assert a RESET.

The product spectrum is designed for supply voltages of 2.5V, 3V, 3.3V, and 5V. The circuits are available in a 6-pin SOT-23 package.

The TPS3813xxx devices are characterized for operation over a temperature range of –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet TPS3813xxx Family Processor Supervisory Circuits With Window-Watchdog datasheet (Rev. J) PDF | HTML 29 Aug 2024
Application note Voltage Supervisors (Reset ICs): Frequently Asked Questions (FAQs) (Rev. A) 17 Mar 2020
Selection guide Voltage Supervisors (Reset ICs) Quick Reference Guide (Rev. H) 28 Feb 2020
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics 28 Jun 2019
EVM User's guide TPS3813XXXEVM for Processor Voltage Supervisor User's Guide 30 Sep 2016
Application note Window Watchdog Calculator for TPS3813 Voltage Supervisors (Rev. A) 13 Sep 2016
Technical article Why monitoring voltages matters PDF | HTML 17 Jun 2015
Application note Choosing an Appropriate Pull-up/Pull-down Resistor for Open Drain Outputs 19 Sep 2011
Application note All Window Watchdog Supervisors 09 Sep 2009

Design & development

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Evaluation board

TPS3813Q1EVM — Evaluation module for the TPS3813-Q1 processor supervisory circuit with window watchdog

The TPS3813-Q1 device is a processor supervisory circuit with watchdog functionality for applications that use DSPs, microcontrollers (MCUs) or microprocessors, or are safety critical. The incorporated window watchdog allows for programmable delay and window ratio that can realease a (...)
User guide: PDF
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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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SOT-23 (DBV) 6 Ultra Librarian

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