首頁 數據轉換器 類比轉數位轉換器 (ADC) 高速 ADC (≥10 MSPS)
首頁
數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12DJ3200QML-SP

現行

抗輻射保證 (RHA)、QMLV、300-krad、12 位元、雙 3.2-GSPS 或單 6.4-GSPS ADC

立即訂購
產品規格表

ADC12DJ3200QML-SP

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CCGA-FC (NWE) 196 225 mm² 15 x 15
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4GSPS in single-channel mode
    • Up to 3.2GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1VPP-DIFF):
    • Dual-channel mode: –149.5dBFS/Hz
    • Single-channel mode: –152.4dBFS/Hz
  • Peak noise power ratio (NPR): 45.4dB
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 7GHz
    • Usable input frequency range: >10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300krad (Si)
    • Single Event Latchup (SEL): 120MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3W
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4GSPS in single-channel mode
    • Up to 3.2GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1VPP-DIFF):
    • Dual-channel mode: –149.5dBFS/Hz
    • Single-channel mode: –152.4dBFS/Hz
  • Peak noise power ratio (NPR): 45.4dB
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 7GHz
    • Usable input frequency range: >10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300krad (Si)
    • Single Event Latchup (SEL): 120MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3W

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200MSPS. In single-channel mode, the device can sample up to 6400MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7GHz, with usable frequencies exceeding the –3dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200MSPS. In single-channel mode, the device can sample up to 6400MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7GHz, with usable frequencies exceeding the –3dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
filter 尋找其它 高速 ADC (≥10 MSPS)
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 10
重要文件 類型 標題 格式選項 日期
* Data sheet ADC12DJ3200QML-SP 6.4GSPS, Single-Channel or 3.2GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. C) PDF | HTML 2025年 3月 21日
* SMD ADC12DJ3200QML-SP SMD ADC12DJ3200QML-SP SMD 5962-18209 2020年 8月 4日
* Radiation & reliability report ADC12DJ3200QML-SP - Single-Event Effects (SEE) Radiation Test Report 2020年 8月 3日
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012年 5月 4日
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025年 6月 17日
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025年 6月 10日
Selection guide TI Space Products (Rev. K) 2025年 4月 4日
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025年 2月 20日
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022年 10月 19日
Technical article How SHP in plastic packaging addresses 3 key space application design challenges PDF | HTML 2022年 10月 17日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADC12DJ3200EVMCVAL — ADC12DJ3200QML-SP 評估模組

ADC12DJ3200 評估模組 (EVM) 專為評估 ADC12DJ3200QML-SP 高速類比轉數位轉換器 (ADC) 所設計。本 EVM 搭載 ADC12DJ3200QML-SP 晶片，該晶片為航太等級、具備 JESD204B 介面的 12 位元、雙通道 4GSPS 或單通道 8GSPS ADC。
使用指南: PDF
TI.com 無法提供
韌體

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

支援產品和硬體

支援產品和硬體
要求
支援軟體

SLVC806 — Xilinx AlphaData Demo

支援產品和硬體

支援產品和硬體
下載
模擬型號

ADC12DJ3200 and ADC12DJ3200QML-SP IBIS and IBIS-AMI Model

SLVMDV3.ZIP (47828 KB) - IBIS-AMI Model
下載
模擬型號

ADC12DJ3200QML-SP S-Parameter Model

SLVMDU7.ZIP (9 KB) - S-Parameter Model
下載
組裝圖

ADC12DJ3200QML-EVM Assembly Package

SLVRBF5.ZIP (4838 KB)
下載
Gerber 檔案

ADC12DJ3200EVMCVAL Design Files

SLVC819.ZIP (4838 KB)
下載
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
要求
封裝 針腳 CAD 符號、佔位空間與 3D 模型
CCGA-FC (NWE) 196 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片