產品規格表
PCA9515B
- Two-Channel Bidirectional Buffers
- I2C Bus and SMBus Compatible
- Support for I2C Standard Mode (100-kHz) and
Fast Mode (400-kHz) - Active-High Repeater-Enable Input
- Open-Drain I2C Input and Output
- 5.5-V Tolerant I2C Input and Output and
Enable Input Support Mixed-Mode Signal Operation - Lockup-Free Operation
- Accommodates Standard Mode, Fast Mode I2C
Devices, and Multiple Masters - Supports Arbitration and Clock Stretching Across
Repeater - Powered-Off High-Impedance I2C Pins
- Latch-Up Performance Exceeds 100-mA Per
JESD 78, Class I - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
The PCA9515B is a BiCMOS dual bidirectional buffer integrated circuit intended for I2C bus and SMBus applications. The device contains two identical bidirectional open-drain buffer circuits that enables I2C and similar bus systems to be extended (or add slaves) without degrading system performance. The dual bidirectional I2C buffer is operational at 2.3 V to 3.6 V VCC.
The PCA9515B buffers both the serial data (SDA) and serial clock (SCL) signals on the I2C bus, while retaining all the operating modes and features of the I2C system. The device allows two buses, of 400-pF bus capacitance, to be connected in an I2C application.
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檢視所有 11 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | PCA9515B Dual Bidirectional I2C Bus and SMBus Repeater datasheet (Rev. B) | PDF | HTML | 2016年 3月 24日 |
| Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024年 7月 3日 | |
| Application note | Why, When, and How to use I2C Buffers | 2018年 5月 23日 | ||
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Choosing the Correct I2C Device for New Designs | PDF | HTML | 2016年 9月 7日 | |
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| Application note | Understanding the I2C Bus | PDF | HTML | 2015年 6月 30日 | |
| Application note | Maximum Clock Frequency of I2C Bus Using Repeaters | 2015年 5月 15日 | ||
| Application note | I2C Bus Pull-Up Resistor Calculation | PDF | HTML | 2015年 2月 13日 | |
| Application note | Programming Fun Lights With TI's TCA6507 | 2007年 11月 30日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 |
設計與開發
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設計工具
I2C-DESIGNER — I2C 設計工具
Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard (...)
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。