SN74AUP1G17
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
(ICC = 0.9 µA Maximum) - Low Dynamic-Power Consumption
(Cpd = 4.4 pF Typical at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot
<10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Includes Schmitt-Trigger Inputs
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 5.1 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
The AUP family of devices is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity).
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | SN74AUP1G17 Low-Power Single Schmitt-Trigger Buffer datasheet (Rev. J) | PDF | HTML | 2017年 9月 29日 |
Application brief | Debounce a Switch | PDF | HTML | 2020年 10月 8日 | |
Application brief | Understanding Schmitt Triggers (Rev. A) | PDF | HTML | 2019年 5月 22日 | |
Selection guide | Little Logic Guide 2018 (Rev. G) | 2018年 7月 6日 | ||
Application note | Designing and Manufacturing with TI's X2SON Packages | 2017年 8月 23日 | ||
Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
Application note | How to Select Little Logic (Rev. A) | 2016年 7月 26日 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 |
設計與開發
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5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
TIDA-00377 — 採用 MOSFET 的自我供電 AC 固態繼電器參考設計
TIDA-00268 — Thunderbolt™ 單連接埠週邊設備參考設計
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
DSBGA (YFP) | 4 | Ultra Librarian |
DSBGA (YZP) | 5 | Ultra Librarian |
SOT-23 (DBV) | 5 | Ultra Librarian |
SOT-5X3 (DRL) | 5 | Ultra Librarian |
SOT-SC70 (DCK) | 5 | Ultra Librarian |
USON (DRY) | 6 | Ultra Librarian |
X2SON (DPW) | 5 | Ultra Librarian |
X2SON (DSF) | 6 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點