TMUX7221
- Latch-up immune
- Dual supply range: ±4.5 V to ±22 V
- Single supply range: 4.5 V to 44 V
- Low on-resistance: 2.1 Ω
- –40°C to +125°C operating temperature
- 1.8 V logic compatible
- Integrated pull-down resistor on logic pins
- Fail-safe logic
- Rail-to-rail operation
- Bidirectional operation
The TMUX722x are complementary metal-oxide semiconductor (CMOS) switches with latch-up immunity in a dual channel, 1:1 (SPST) configuration. These devices work with a single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX722x supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.
The TMUX722x can be enabled or disabled by controlling the SEL pins, turning on signal path 1 (S1 to D1) or signal path 2 (S2 to D2). All logic control inputs support logic levels from 1.8 V to VDD, allowing for both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-safe logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. For more information, see .
The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TMUX722x 44 V , Low-RON, 1:1 (SPST), 2-Channel Precision Switches with Latch-Up Immunity and 1.8-V Logic datasheet (Rev. B) | PDF | HTML | 2024年 5月 6日 |
EVM User's guide | TMUX10DGS Evaluation Module User's Guide | PDF | HTML | 2024年 4月 9日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
TMUX-10DGS-EVM — TMUX 10-DGS 評估模組
TMUX-10DGS-EVM 用於評估 10 針腳 DGS 封裝的性能。評估模組 (EVM) 隨附一個板,可焊接 10 針腳 DGS 裝置。此外也提供板載測試點,可以彈性地測試各種訊號。
LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VSSOP (DGS) | 10 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。