TPSI2140-Q1
- Qualified for automotive applications
- AEC-Q100 grade 1: –40 to 125°C T A
- Integrated avalanche rated MOSFETs
- Designed and qualified for reliability during overvoltage conditions, including system level dielectric withstand testing (Hi-Pot)
- I AVA = 2-mA for 5-s pulses, 1-mA for 60-s pulses
- 1200-V standoff voltage
- R ON = 130-Ω (T J = 25°C)
- T ON, T OFF < 700-µs
- Designed and qualified for reliability during overvoltage conditions, including system level dielectric withstand testing (Hi-Pot)
- Low primary side supply current
- 9-mA ON state current
- 3.5-µA OFF state current
- Functional Safety Capable
- Documentation available to aid in ISO 26262 and IEC 61508 system design
- Robust isolation barrier:
- > 26 year projected lifetime at 1000-V RMS / 1500-V DC working voltage
- Isolation rating, V ISO, up to 3750-V RMS / 5300-V DC
- Peak surge, V IOSM, up to 5000-V
- ± 100-V/ns typical CMTI
- SOIC 11-pin (DWQ) package with wide pins for improved thermal performance
- Creepage and clearance ≥ 8-mm (primary-secondary)
- Creepage and clearance ≥ 6-mm (across switch terminals)
- Safety-related certifications
- (Planned) DIN VDE V 0884-11:2017-01
- (Planned) UL 1577 component recognition program
The TPSI2140-Q1 is an isolated solid state relay designed for high voltage automotive and industrial applications. The TPSI2140-Q1 uses TIs high reliability capacitive isolation technology in combination with internal back-to-back MOSFETs to form a completely integrated solution requiring no secondary side power supply.
The primary side of the device is powered by only 9 mA of input current and incorporates a fail-safe EN pin preventing any possibility of back powering the VDD supply. In most applications, the VDD pin of the device should be connected to a system supply between 5 V–20 V and the EN pin of the device should be driven by a GPIO output with logic HI between 2.1 V–20 V. In other applications, The VDD and EN pins could be driven together directly from the system supply or from a GPIO output. All control configurations of the TPSI2140-Q1 do not require additional external components such as a resistor and/or low side switch that are typically required in photo relay solutions.
The secondary side consists of back-to-back MOSFETs with a standoff voltage of ±1.2 kV from S1 to S2. The TPSI2140-Q1 MOSFETs avalanche robustness and thermally conscious package design allow it to robustly support system level dielectric withstand testing (HiPot) and DC fast charger surge currents of up to 2 mA without requiring any external components.
技術文件
設計與開發
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TPSI2140Q1EVM — TPSI2140-Q1 評估模組,適用具有 2-mA 雪崩擊穿額定值的 1200-V、50-mA 隔離開關
TPSI2140Q1EVM 評估模組是包含多個測試點和跳線的雙銅層電路板,以全面評估裝置功能。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TIDA-010232 — 隔離監控採用高電壓 EV 充電和太陽能的 AFE 參考設計
TIDA-01513 — 車用高電壓與隔離洩漏測量參考設計
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOIC (DWQ) | 11 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。