This reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2Gx Multicore DSP + ARM processor System-on-Chip (SoC). It enables developers to implement a high reliability based solution rapidly by discussing system interfaces, board hardware, software, throughput performance and diagnostic procedures.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Files used for 3D models or 2D drawings of IC components
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx-Based Systems (Rev. B) | Jun. 12, 2018 | |
| Design guide | PCI-Express PCB Design Considerations for the K2Gx GP EVM Design Guide (Rev. A) | Jun. 12, 2018 |
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