The TIDEP0079 reference design demonstrates an EtherCAT® master interface running on the Sitara™ AM572x processor using the EC-Master stack from acontis. This EtherCAT master solution can be used for EtherCAT-based PLC or motion control applications. EtherCAT master is profiled on both the Ethernet switch and the PRU-ICSS Ethernet ports of the AM572x processor to give designers flexibility to use any of the two switch ports or four PRU-ICSS Ethernet ports on the device. The EtherCAT master implementation can achieve less than 100µs cycle times for both the switch and the PRU-ICSS Ethernet ports. Time-triggered send (TTS) can be enabled on the PRU-ICSS to reduce jitter, achieve shorter cycle times, and reduce latency in cases where distributed clocking is not used.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
Design file that contains information on physical board layer of design PCB
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | TIDEP0079 Design Guide (Rev. B) | Oct. 26, 2016 | |
| Technical article | Rise of the industrial robots. Overcoming the challenges of safe robot-human-inter | PDF | HTML | Nov. 08, 2016 |
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