DLPS112C June   2018  – August 2021 DLPC3479

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 PDATA Bus – Parallel Interface Bit Mapping Modes
      2. 7.3.2  Pattern Display
        1. 7.3.2.1 External Pattern Mode
          1. 7.3.2.1.1 8-bit Monochrome Patterns
          2. 7.3.2.1.2 1-Bit Monochrome Patterns
        2. 7.3.2.2 Internal Pattern Mode
          1. 7.3.2.2.1 Free Running Mode
          2. 7.3.2.2.2 Trigger In Mode
      3. 7.3.3  Device Start-Up
      4. 7.3.4  SPI Flash
        1. 7.3.4.1 SPI Flash Interface
        2. 7.3.4.2 SPI Flash Programming
      5. 7.3.5  I2C Interface
      6. 7.3.6  Content Adaptive Illumination Control (CAIC)
      7. 7.3.7  Local Area Brightness Boost (LABB)
      8. 7.3.8  3D Glasses Operation
      9. 7.3.9  Test Point Support
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
      3. 11.1.3 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision B (May 2019) to Revision C (August 2021)

  • Changed Pixel Clock to 155 MHz Go
  • Updated the numbering format for tables, figures, and cross-references throughout the document. Go
  • Reorganized Pin Function descriptions Go
  • Changed JTAG pin names from Reserved to proper names Go
  • Deleted support for adjustable DATAEN_CMD polarity Go
  • Deleted mention of a specific 3D command Go
  • Deleted support for adjusting PCLK capture edge in software Go
  • Changed table "Pin Functions - Peripheral Interface" Go
  • Changed the description of how to use the CMP_OUT pin and corrected how the comparator must use GPIO_10 (RC_CHARGE) instead of CMP_PWM Go
  • Deleted support for CMP_PWMGo
  • Added note about VCC_INTF power up recommendations if target devices are on the I2C bus Go
  • Changed table "Pin Functions - GPIO Peripheral Interface" Go
  • Changed description for GPIO_02 (removed option 2) Go
  • Changed description for GPIO_01 (removed option 2) Go
  • Deleted table "GPIO_01 and GPIO_02" Go
  • Changed table "Pin Functions - Clock and PLL Support" Go
  • Changed table "Pin Functions - Power and Ground" Go
  • Changed table "I/O Type Subscript Definition" Go
  • Updated Absolute Maximum Rating Go
  • Updated Recommended Operating Conditions Go
  • Deleted row for VDDLP12 Go
  • Updated V(VCC18) maximum from 18 mA to 62 mA in Section 6.5 Go
  • Updated V(VCC18) + V(VCC_INTF) + V(VCC_FLSH) maximum from 22.5 mA to 66.5 mA in Section 6.5 Go
  • Changed Power Electrical Characteristics table to reflect updated power measurement values and techniques Go
  • Deleted reference to unsupported IDLE mode Go
  • Added note that the power numbers vary depending on the utilized softwareGo
  • Changed and fixed incorrect test conditions for current drive strengthsGo
  • Deleted redundant ǀVODǀ specification which is referenced in later sectionsGo
  • Added minimum and maximum values for VOH for I/O type 4Go
  • Added minimum and maximum values for VOL for I/O type 4Go
  • Deleted incorrect reference to 2.5V, 24mA drive Go
  • Corrected I2C buffer test conditionsGo
  • Deleted incorrect steady-state common mode voltage reference Go
  • Changed high voltage tolerant I/O note to only refer to the I2C buffer and changed VCC to VCC_INTF.Go
  • Added |VOD| minimum and maximum values, and changed the typical value.Go
  • Added high-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted redundant mention of specification, and changed the typical value. Go
  • Added low-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted redundant mention of specification, and changed the typical value. Go
  • Corrected the name of the DMD Low-Speed signals from inputs to outputs. Go
  • Deleted VOH(DC) maximum and VOL(DC) minimum values. Go
  • Added note about DMD input specs being met if a proper series termination resistor is used Go
  • Deleted reference of selecting unsupported oscillator frequency Go
  • Corrected system oscillator clock period to match clock frequency Go
  • Changed pulse duration percent spec from a maximum to a minimum Go
  • Added condition for VDD rise time Go
  • Deleted the incorrect part of the tp_tvb definitionGo
  • Deleted unneeded total horizontal blanking equation Go
  • Changed minimum total vertical blanking equation Go
  • Increased maximum PCLK from 150 MHz to 155MHz Go
  • Deleted reference to various signal's active edges being configurable Go
  • Changed the minimum flash SPI_CLK frequencyGo
  • Corrected flash interface clock period to match clock frequency Go
  • Added Section 6.15 section to more clearly list signal transition time requirementsGo
  • Changed DMD HS Clock switching rate from maximum to nominal and added accompanying clock specification Go
  • Added Section 6.17 Go
  • Added Section 6.18 to clarify chipset support requirementsGo
  • Added information that the parallel interface isn't ready to accept data until the auto-initialization process is completedGo
  • Changed how the 500 ms startup time is described Go
  • Changed SPI flash key timing parameter access frequency minimum and maximum valuesGo
  • Included additional DLPC3479 compatible SPI flash device options in Table 7-7 Go
  • Changed maximum flash size supported from 16Mb to 128Mb Go
  • Deleted SPI signal routing section Go
  • Deleted support for a light sensor integrated with the DLPC34xx controller Go
  • Added Section 7.3.8 Go
  • Added missing timing definitions Go
  • Clarified that the mentioned SDR clock speed is the typical valueGo
  • Changed which signals are listed as tri-stated at power up and which signals are pulled low Go
  • Changed 1-oz copper plane recommendation Go
  • Deleted reference to unsupported option of variable frequency reference clockGo
  • Added additional DMD data and DMD clock signal matching requirements Go
  • Changed maximum mismatch from ±0.1" to ±1.0" Go
  • Changed incorrect signal matching requirement table noteGo
  • Changed differential signal layer change to a recommendationGo
  • Changed wording requiring no more than two vias on certain DMD signals Go

Changes from Revision A (February 2019) to Revision B (May 2019)

  • Changed normal park time from 500 μs to 20 msGo