SBOS027C September   2000  – September 2022 INA118

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Noise Performance
      2. 8.4.2 Input Common-Mode Range
      3. 8.4.3 Input Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting the Gain
        2. 9.2.2.2 Dynamic Performance
        3. 9.2.2.3 Offset Trimming
        4. 9.2.2.4 Input Bias Current Return Path
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Low-Voltage Operation
      2. 9.3.2 Single-Supply Operation
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision B (April 2019) to Revision C (September 2022)

  • Remove "a newer version of this device is now available: INA818" text from titleGo
  • Changed minimum supply voltage from ±1.35 V to ±2.25 V and from 2.7 V to 4.5 V throughout documentGo
  • Changed Applications to link to latest end-equipment on ti.comGo
  • Changed minimum supply voltage from ±1.35 V to ±2.25 VGo
  • Changed resistors in Simplified Schematic from 60 kΩ to 40 kΩGo
  • Changed minimum and maximum input common-mode voltage from V– + 1.1 V and V+ – 1 V to V– + 2 V and V+ – 2 V respectively in Recommended Operating Conditions Go
  • Changed minimum and maximum ambient temperature from –55°C and +150°C to –40°C and +125°C respectively in Recommended Operating Conditions Go
  • Added VCM = 0 V to test conditions below title in Electrical Characteristics Go
  • Changed input offset voltage vs temperature test condition from TA = TMIN to TMAX to TA = –40°C to +85°C in Electrical Characteristics Go
  • Changed input offset voltage vs power supply test condition from VS = ±1.35 V to ±18 V to VS = ±2.25 V to ±18 V in Electrical Characteristics Go
  • Changed high-side linear input voltage range from (V+) – 1 V minimum and (V+) – 0.65 V typical to (V+) – 2 V minimum and (V+) – 1.4 V typical in Electrical Characteristics Go
  • Changed low-side linear input voltage range from (V–) + 1.1 V minimum and (V–) + 0.95 V typical to (V–) + 2 V minimum and (V–) + 1.2 V typical in Electrical Characteristics Go
  • Added test condition of TA = –40°C to +85°C to bias current vs temperature and offset current vs temperature in Electrical Characteristics Go
  • Added test condition of TA = –40°C to +85°C to gain vs temperature and 50-kΩ resistance vs temperature in Electrical Characteristics Go
  • Changed single supply output voltage test condition from VS = 2.7 V/0 V to V+ = 4.5 V, V– = 0 V in Electrical Characteristics Go
  • Deleted power supply voltage range specification from Electrical Characteristics Go
  • Deleted temperature range specifications from Electrical Characteristics Go
  • Changed Figures 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-11, 7-12, 7-18, 7-19, and 7-20 in Typical Characteristics Go
  • Changed FET transistor input current limit from approximately 1.5-5 mA to 6 mA in Overview Go
  • Deleted internal node equations in Overview and Functional Block Diagram Go
  • Changed schematic in Functional Block Diagram Go
  • Changed linear input voltage range in Input Common-Mode Range and Single-Supply Operation Go
  • Changed FET transistor input current limit from approximately 1.5-5 mA to 6 mA in Input Protection Go
  • Changed resistors in Figure 9-1 from 60 kΩ to 40 kΩ in Typical Application Go
  • Changed minimum supply voltage from ±1.35 V to ±2.25 V in Low-Voltage Operation Go
  • Changed minimum supply voltage from 2.7 V to 4.5 V in Single-Supply Operation Go
  • Changed input common-mode range description in Single-Supply Operation Go
  • Changed Figure 10-5 to use a 5-V supply voltageGo

Changes from Revision A (January 2016) to Revision B (April 2019)

  • Added information about the newer, upgraded INA818 Go
  • Added Device Comparison Table Go

Changes from Revision * (September 2000) to Revision A (January 2016)

  • Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go