SLVS632K January   2006  – January 2024 TPS5430 , TPS5431

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information (DDA Package)
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Oscillator Frequency
      2. 6.3.2  Voltage Reference
      3. 6.3.3  Enable (ENA) and Internal Slow Start
      4. 6.3.4  Undervoltage Lockout (UVLO)
      5. 6.3.5  Boost Capacitor (BOOT)
      6. 6.3.6  Output Feedback (VSENSE) and Internal Compensation
      7. 6.3.7  Voltage Feed-Forward
      8. 6.3.8  Pulse-Width-Modulation (PWM) Control
      9. 6.3.9  Overcurrent Limiting
      10. 6.3.10 Overvoltage Protection
      11. 6.3.11 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation near Minimum Input Voltage
      2. 6.4.2 Operation with ENA control
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 12-V Input to 5.0-V Output
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Switching Frequency
          3. 7.2.1.2.3 Input Capacitors
          4. 7.2.1.2.4 Output Filter Components
            1. 7.2.1.2.4.1 Inductor Selection
            2. 7.2.1.2.4.2 Capacitor Selection
          5. 7.2.1.2.5 Output Voltage Set-Point
          6. 7.2.1.2.6 BOOT Capacitor
          7. 7.2.1.2.7 Catch Diode
          8. 7.2.1.2.8 Advanced Information
            1. 7.2.1.2.8.1 Output Voltage Limitations
            2. 7.2.1.2.8.2 Internal Compensation Network
            3. 7.2.1.2.8.3 Thermal Calculations
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Wide Input Voltage Ranges with TPS5430
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Wide Input Voltage Ranges with TPS5431
          1. 7.2.2.3.1 Design Requirements
          2. 7.2.2.3.2 Detailed Design Procedure
      3. 7.2.3 Circuit Using Ceramic Output Filter Capacitors
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
          1. 7.2.3.2.1 Output Filter Component Selection
          2. 7.2.3.2.2 External Compensation Network
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision J (July 2022) to Revision K (January 2024)

  • Updated WEBENCH® links throughout the data sheet. Added "integrated circuit" when the PowerPAD™ package is mentioned. Changed MOSFET resistance 110mΩ to100mΩ. Changed I Q from 18μA to 15μAGo
  • Changed Pin Configuration figure title to "DDA Package 8-Pin SOIC with Thermal Pad Top View" and repositioned the title to the correct position. Changed "PowerPAD" to "DAP". Go
  • Updated Absolute Maximum Ratings table to new format which does not include specific parameter names and does include min and max columns. TJ called out in header.  Pin names are used rather than signal names.  BOOT and PH voltages now marked as output voltage. Updated footnotes and removed Note 2.Go
  • Changed BOOT to PH Absolute Maximum from 10 V to 6 V.Go
  • Changed PH to GND Absolute Maximum (transient < 10 ns) from -4 V to -1.2 V.Go
  • Changed CDM ESD from ±1500 V to ±750 VGo
  • Changed recommended operating "VI" to "input voltage".Go
  • Updated thermal information footnotes to match current TI standards which include JEDEC standard information.  Changed custom board information to EVM RθJA information.Go
  • Changed RθJC(top)  from 46.4 to 46, RθJB from 20.8 to 15, ψJT from 4.9 to 5.2, ψJB from 20.7 to 15.3, and RθJC(bot) from 0.8 to 6.Go
  •  Added condition for typical specifications EC table’s header, added parameter names, and used pin names in parameter descriptions.  Footnote added.Go
  • Changed test condition for VFB from “IO = 0 A to 3 A” to “TJ = –40°C to 125°C”, Changed rDS(ON) to RDSON(HS) and test condition to for RDSON(HS) from “VIN = 5.5 V” to “VIN = 5.5 V, VBOOT-SW = 4.0 V”.Go
  • Changed the name of IQ to ISD(VIN) if ENA is low and IQ(VIN) if the chip is active.Go
  • Added test condition for DMAX, “fSW = 500 kHz” and for second RDSON(HS) spec “VIN = 12 V, VBOOT-SW = 4.5 V”.Go
  • Changed IQ(VIN) typical from 3 mA to 2 mA, ISD(VIN) typical from 18 µA to 15 µA, VINUVLO(H) from 330 mV to 0.35 V, and VEN(H) from 450 mV to 325 mV.Go
  • Changed RDS(ON) with VIN = 5 V typical from 150 mΩ to 125 mΩ and with VIN = 12 V from 110 mΩ to 100 mΩGo
  • Changed "110-mΩ high-side MOSFET" to "100-mΩ high-side MOSFET" and 18 µA to 15 µA in Overview Go
  • Changed shutdown current from 18 μA to 15 μA in Enable (ENA) and Internal Slow Start sectionGo
  • Changed UVLO hysteresis from 330 mV to 350 mV in UVLO description.Go
  • Changed "PwPd" to "DAP" on the TPS5430DDA package drawing in Figure 7-1 and "exposed PowerPAD™" to DAP in circuit description Go
  • Changed "PwPd" to "DAP" on the TPS5430DDA package drawing in Figure 7-9.Go
  • Changed "PwPd" to "DAP" on the TPS5431DDA package drawing in Figure 7-10.Go
  • Changed "PwPd" to "DAP" on the TPS5430DDA package drawing in Figure 7-11.Go
  • Changed "PowerPAD" to "DAP" in Layout Guidelines Go

Changes from Revision I (April 2017) to Revision J (July 2022)

  • Updated the numbering format for tables, figures, and cross-references throughout the document.Go

Changes from Revision H (April 2016) to Revision I (March 2017)

  • Added WEBENCH® Model Go