SLVSDW6C April   2017  – April 2021 TPS7H1101A-SP

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start
      2. 7.3.2 Power Good (PG)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable/Disable
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Stability
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Adjustable Output Voltage (Feedback Circuit)
        2. 8.2.1.2 PCL
        3. 8.2.1.3 High-Side Current Sense
        4. 8.2.1.4 Current Foldback
        5. 8.2.1.5 Transient Response
        6. 8.2.1.6 Current Sharing
        7. 8.2.1.7 Compensation
        8. 8.2.1.8 Output Noise
        9. 8.2.1.9 Capacitors
      2. 8.2.2 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Current Sharing

For demanding load requirements, multiple LDOs can be paralleled as indicated in Figure 8-12. In parallel mode, the CS terminal of LDO1 must be connected to the PCL terminal of LDO2 via a series resistor, RCL, and CS terminal of LDO2 must be connected to PCL terminal of LDO1 via series resistor, RCL. The typical value of RCL in parallel operation is 3.75 kΩ for current limit > 6 A. In parallel configuration, RCL (resistor from PCL to GND) and RCS (resistor from CS terminal to VIN) must be left open (unpopulated). The RCL value must be selected so that the operating condition of the CS terminal is maintained, as specified in Section 6.5. VCS must be greater than 0.3 V to insure proper current sense operation. The current from PCL through RCL of LDO1 is determined by the output load current of LDO2 divided by the CSR. Hence, the voltage at CS terminal of the LDO1 is 0.605 V – ((output load current of LDO2 + 0.2458) / CSR × RCL).

Alternately, it can also provide twice the output current to meet system needs. When using two LDOs in parallel operation for higher output load current, use POL TPS50601-SP as an input source.

GUID-34F52AEA-8658-472F-8F7B-63FC298B6FD5-low.gifFigure 8-11 LDO Current Share
GUID-6B3103F8-4F36-4436-AE95-5475A0EF1A1D-low.gifFigure 8-12 Block Diagram (Parallel Operation)