SLVSFT8F February 2023 – December 2023 TPS7H1111-SEP , TPS7H1111-SP
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
This device is designed to operate with an input voltage supply from 0.85 V to 7 V. The minimum input voltage must provide adequate headroom greater than the dropout voltage for the device to have a regulated output. Additionally, a separate BIAS supply is normally used in order to reduce dropout voltage. The bias supply voltage range is from 2.2 V to 14 V (and at least as high as the input voltage supply); however, for optimal performance, it is recommended VBIAS ≥ VOUT + 1.6 V. For additional information view Section 8.3.1.
The internal power dissipation during device regulation, PD, can be approximated using Equation 19.
The TPS7H1111 is a high-PSRR device. In order to obtain the full benefits of the high PSRR from VIN to VOUT, it is important that VBIAS at the BIAS pin input is clean. Any ripple on the BIAS pin will couple from VBIAS to VOUT (reduced by PSRRBIAS). The best way to ensure BIAS sees a clean input is to add an RC filter before the BIAS pin. Due to the limited current the BIAS pin consumes, the voltage drop across the resistor is generally acceptable. A suggested value for the RC filter is R = 10 Ω and C = 4.7 μF.
A bulk input capacitor of 10 μF with a 0.1 μF ceramic decoupling capacitor is generally sufficient for good performance. If the input supply is far away from the input of the TPS7H1111, a larger input capacitor such as 47 μF or 100 μF may be beneficial.
The TPS7H1111 is optimized for a single tantalum output capacitor of 220 μF or two 100 μF capacitors. Additionally, a single 0.1 μF ceramic capacitor may be used. Place the tantalum capacitor(s) near the output of the TPS7H1111 and place the ceramic capacitor near the point of load. See Section 8.3.8.1 for additional information.