SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Recommended Operating Conditions

over operating temperature range, TJ = –55°C to 125°C (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage IN 0.85 7 V
BIAS(1) VIN VOUT + 1.6 V
2.2 14
PG 0 7
EN 0 7
FB_PG 0 6
CLM 0 VIN
Output voltage OUT(2) VIN – VDO V
0.4 5.5
SS_SET(2) VIN – VDO
0.4 5.5
Input current PG 0 0.002 A
Output current OUT 0 1.5 A
Output bulk capacitance(3) COUT 132 200 308 µF
ESR 7 40 mΩ
ESL 0.8 2.4 nH
Reference configuration RREF 11 12 13 kΩ
EN toggle time(4) tEN_LOW 20 µs
Junction temperature TJ –55 125 °C
(1) BIAS has two minimum values, VIN and 2.2 V. BIAS must be set greater than or equal to the larger of these two values. The BIAS max value is always 14 V. For full performance set VBIAS ≥ VOUT + 1.6 V. See the Bias Supply Section for further details.
(2) OUT and SS_SET have two maximum values, (VIN – VDO) and 5.5 V. OUT and SS_SET must be set to less than or equal to the smaller of these two values. The OUT and SS_SET min value is always 0.4 V.
(3) These are the default acceptable output capacitance, equivalent series resistance (ESR), and equivalent series inductance (ESL) values for the bulk capacitance. Other values may be acceptable, such as by modifying the control loop with external compensation using the STAB pin. Tantalum or Tantalum Polymer capacitors are normally used to meet these requirements. Additional ceramic decoupling capacitors are not required, but a single 0.1 µF ceramic capacitor with low ESL near the point of load is acceptable.

Additional larger ceramic capacitors are not needed due to the high PSRR and low noise provided by the TPS7H1111 LDO across a wide bandwidth. Therefore, the TPS7H1111 is not designed to support larger ceramic capacitors. See the Output Capacitance Section for additional information.
(4) tEN_LOW is the time the EN pin must be driven low before again being driven high for the device to detect a reset. This is generally only applicable when attempting to exit turn-off current limit mode.