JAJSD74E February   2016  – August 2022 ADS8681 , ADS8685 , ADS8689

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.9 Alarm Features

The device features an active-high alarm output on the ALARM/SDO-1/GPO pin, provided that the pin is configured for alarm functionality. To enable the ALARM output on the multifunction pin, see the SDO1_CONFIG[1:0] bits of the SDO_CTL_REG register to 01b (see the SDO_CTL_REG register).

The device features two types of alarm functions: an input alarm and an AVDD alarm.

  • For the input alarm, the voltage at the input of the ADC is monitored and compared against user-programmable high and low threshold values. The device sets an active high alarm output when the corresponding digital value of the input signal goes beyond the high or low threshold set by the user; see the Section 7.3.9.1 section for a detailed explanation of the input alarm feature functionality.
  • For the AVDD alarm, the analog supply voltage (AVDD) of the ADC is monitored and compared against the specified typical low threshold (4.7 V) and high threshold (5.3 V) values of the AVDD supply. The device sets an active high alarm output if the value of AVDD crosses the specified low (4.7 V) and high threshold (5.3 V) values in either direction.

When the alarm functionality is turned on, both the input and AVDD alarm functions are enabled by default. These alarm functions can be selectively disabled by programming the IN_AL_DIS and VDD_AL_DIS bits (respectively) of the RST_PWRCTL_REG register.

Each alarm (input alarm or AVDD alarm) has two associated types of alarm flags: the active alarm flag and the tripped alarm flag. All the alarm flags can be read in the ALARM_REG register. Both flags are set when the associated alarm is triggered. However while the active alarm is cleared at the end of the current ADC conversion (and set again if the alarm condition persists), the tripped flag is cleared only after ALARM_REG is read.

The ALARM output flags are updated internally at the end of every conversion. These output flags can be read during any data frame that the user initiates by bringing the CONVST/CS signal to a low level.

The ALARM output flags can be read in three different ways: either via the ALARM output pin, by reading the internal ALARM registers, or by appending the ALARM flags to the data output.

  • A high level on the ALARM pin indicates an over- or undervoltage condition on AVDD or on the analog input channel of the device. This pin can be wired to interrupt the host input.
  • The internal ALARM flag bits in the ALARM_REG register are updated at the end of conversion. After receiving an ALARM interrupt on the output pin, the internal alarm flag registers can be read to obtain more details on the conditions that generated the alarm.
  • The alarm output flags can be selectively appended to the data output bit stream (see the DATAOUT_CTL_REG register for configuration details).

Figure 7-20 depicts a functional block diagram for the device alarm functionality.

GUID-843925DA-6F39-410D-8877-C34A1952984C-low.gifFigure 7-20 Alarm Functionality Schematic