JAJSH89D May 2012 – April 2019 CDCUN1208LP
PRODUCTION DATA.
The CDCUN1208LP supports Edge Rate Control (ERC), to tailor jitter and EMI performance from device outputs. Table 3 shows the edge rate control setting. This setting affects all device outputs equally. Each edge rate setting is unique to the output buffer type selected as described in Clock Output Buffer Characteristics (Output Mode = LVDS), Clock Output Buffer Characteristics (Output Mode = HCSL), and Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS).
ERC (Pin 31) | OUTPUT EDGE RATE |
---|---|
LOW | SLOW |
HIGH | MEDIUM |
OPEN | FAST |