JAJSGV8B September 2019 – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The control registers are used to configure the device. The control registers are read and write capable.
Table 27 lists the memory-mapped registers for the control registers. All register offset addresses not listed in Table 27 should be considered as reserved locations and the register contents should not be modified.
Address | Register Name | Section |
---|---|---|
0x07 | Configuration Register | Go |
0x08 | Operation Control 1 Register | Go |
0x09 | Operation Control 2 Register | Go |
0x0A | Operation Control 3 Register | Go |
0x0B | PWM Control 1 Register | Go |
0x0C | PWM Control 2 Register | Go |
0x0D | Free-Wheeling Control 1 Register | Go |
0x0E | Free-Wheeling Control 2 Register | Go |
0x0F | PWM Map Control 1 Register | Go |
0x10 | PWM Map Control 2 Register | Go |
0x11 | PWM Map Control 3 Register | Go |
0x12 | PWM Frequency Control Register | Go |
0x13 | PWM Duty Control Channel 1 Register | Go |
0x14 | PWM Duty Control Channel 2 Register | Go |
0x15 | PWM Duty Control Channel 3 Register | Go |
0x16 | PWM Duty Control Channel 4 Register | Go |
0x17 | Slew Rate Control 1 Register | Go |
0x18 | Slew Rate Control 2 Register | Go |
0x19 | Open-Load Detect Control 1 Register | Go |
0x1A | Open-Load Detect Control 2 Register | Go |
0x1B | Open-Load Detect Control 3 Register | Go |
0x24 | Open-Load Detect Control 4 Register | Go |