SNLS231P September   2006  – August 2024 DS90UR124-Q1 , DS90UR241-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Serializer Input Timing Requirements for TCLK
    7. 5.7 Serializer Switching Characteristics
    8. 5.8 Deserializer Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Initialization and Locking Mechanism
      2. 6.3.2  Data Transfer
      3. 6.3.3  Resynchronization
      4. 6.3.4  Powerdown
      5. 6.3.5  Tri-State
      6. 6.3.6  Pre-Emphasis
      7. 6.3.7  AC-Coupling and Termination
        1. 6.3.7.1 Receiver Termination Option 1
        2. 6.3.7.2 Receiver Termination Option 2
        3. 6.3.7.3 Receiver Termination Option 3
      8. 6.3.8  Signal Quality Enhancers
      9. 6.3.9  @SPEED-BIST Test Feature
      10. 6.3.10 Backward-Compatible Mode With DS90C241 and DS90C124
    4. 6.4 Device Functional Modes
  8.   Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Using the DS90UR241 and DS90UR124
      2. 7.1.2 Display Application
      3. 7.1.3 Typical Application Connection
    2. 7.2 Typical Applications
      1. 7.2.1 DS90UR241-Q1 Typical Application Connection
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Power Considerations
          2. 7.2.1.2.2 Noise Margin
          3. 7.2.1.2.3 Transmission Media
          4. 7.2.1.2.4 46
          5. 7.2.1.2.5 Live Link Insertion
        3. 7.2.1.3 Application Curves
      2. 7.2.2 DS90UR124 Typical Application Connection
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout and Power System Considerations
        2. 7.4.1.2 LVDS Interconnect Guidelines
      2. 7.4.2 Layout Examples
  9. 7Device and Documentation Support
    1. 7.1 Device Support
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Support Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  10. 8Revision History
  11.   Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
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4 Pin Configuration and Functions

DS90UR124-Q1 DS90UR241-Q1 PFB Package48-Pin TQFPTop View Figure 4-1 PFB Package
48-Pin TQFP
Top View
Table 4-1 Pin Functions: PFB Package
PIN I/O DESCRIPTION
NO. NAME
LVCMOS PARALLEL INTERFACE PINS
4-1, 48-44, 41-32, 29-25 DIN[23:0] LVCMOS_I Transmitter Parallel Interface Data Input Pins. Tie LOW if unused; do not float.
10 TCLK LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
CONTROL AND CONFIGURATION PINS
18 DEN LVCMOS_I Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-) Outputs are in Tri-state, PLL still operational and locked to TCLK.
23 PRE LVCMOS_I Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor RPRE. Resistor value determines pre-emphasis level. Recommended value RPRE ≥ 6kΩ; Imax = [48 / RPRE], RPREmin = 6kΩ
12 RAOFF LVCMOS_I Randomizer Control Input Pin
RAOFF = H, Backwards compatible mode for use with DS90C124 Deserializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
See Table 6-1 for more details.
5, 8, 13 RES0 LVCMOS_I Reserved. This pin must be tied LOW.
9 TPWDNB LVCMOS_I Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are in Tri-state stand-by mode, PLL is shutdown to minimize power consumption.
11 TRFB LVCMOS_I Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge.
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
24 VODSEL LVCMOS_I VOD Level Select
VODSEL = L; LVDS Driver Output is ±500 mV (RL = 100Ω)
VODSEL = H; LVDS Driver Output is ±900 mV (RL = 100Ω)
For normal applications, set this pin LOW. For long cable applications where a larger VOD is required, set this pin HIGH.
LVDS SERIAL INTERFACE PINS
20 DOUT+ LVDS_O Transmitter LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the DOUT+ pin. The interconnect must be AC coupled to this pin with a 100nF capacitor.
19 DOUT− LVDS_O Transmitter LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the DOUT- pin. The interconnect must be AC coupled to this pin with a 100nF capacitor.
POWER / GROUND PINS
22 VDD VDD Analog Voltage Supply, LVDS Output POWER
16 VDD VDD Analog Voltage Supply, VCO POWER
14 VDD VDD Analog Voltage Supply, PLL POWER
30 VDD VDD Digital Voltage Supply, Serializer POWER
7 VDD VDD Digital Voltage Supply, Serializer Logic POWER
42 VDD VDD Digital Voltage Supply, Serializer INPUT POWER
21 VSS GND Analog Ground, LVDS Output GROUND
17 VSS GND Analog Ground, VCO GROUND
15 VSS GND Analog Ground, PLL GROUND
31 VSS GND Digital Ground, Serializer GROUND
6 VSS GND Digital Ground, Serializer Logic GROUND
43 VSS GND Digital Ground, Serializer Input GROUND
DS90UR124-Q1 DS90UR241-Q1 PAG Package64-Pin TQFPTop View Figure 4-2 PAG Package
64-Pin TQFP
Top View
Table 4-2 Pin Functions: PAG Package
PIN I/O DESCRIPTION
NO. NAME
LVCMOS PARALLEL INTERFACE PINS
24 RCLK LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
35-38, 41-44 ROUT[7:0] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 1
19-22, 27-30 ROUT[15:8] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 2
7-10, 13-16 ROUT[23:16] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 3
CONTROL AND CONFIGURATION PINS
23 LOCK LVCMOS_O LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are at Tri-state.
49 PTOSEL LVCMOS_I Progressive Turn On Operation Selection
PTO = H; ROUT[23:0] are grouped into three groups of eight, with each group switching about ±1 UI to ±2 UI apart relative to RCLK. (Figure 5-15)
PTO = L; PTO Spread Mode, ROUT[23:0] outputs are spread ±1 UI to ±2 UI and RCLK spread ±1 UI. (Figure 5-16) See Applications Information section for more details.
63 RAOFF LVCMOS_I Randomizer Control Input Pin (See Table 2 for more details.)
RAOFF = H, Backwards compatible mode for use with DS90C241 Serializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
60 REN LVCMOS_I Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs are in Tri-state, PLL still operational and locked to TCLK.
50 RES0 LVCMOS_I Reserved. This pin MUST be tied LOW.
1-6, 17, 18, 33, 34 RES0 NC No Connection. Pins are not physically connected to the die. Recommendation is to leave pin open or tie to LOW.
48 RPWDNB LVCMOS_I Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), ROUT[23-0], RCLK, and LOCK are in Tri-state standby mode, PLL is shutdown to minimize power consumption.
55 RRFB LVCMOS_I Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
64 SLEW LVCMOS_I LVCMOS Output Slew Rate Control
SLEW = L; Low drive output at 2mA (default)
SLEW = H; High drive output at 4mA
BIST MODE PINS (See Section 7 for more details.)
61 BISTEN LVCMOS_I Control Pin for BIST Mode Enable
BISTEN = L; Default at Low, Normal Mode.
BISTEN = H; BIST mode active. When BISTEN = H and DS90UR241 DIN[23:0] = Low or Floating; device goes to BIST mode accordingly. Check PASS output pin for test status.
62 BISTM LVCMOS_I BIST Mode selection. Control pin for which Deserializer is set for BIST reporting mode.
BISTM = L; Default at Low, Status of all ROUT with respective bit error on cycle-by-cycle basis
BISTM = H; Total accumulated bit error count provided on ROUT[7:0] (binary counter up to 255)
45 PASS LVCMOS_O Pass flag output for @Speed BIST Test operation.
PASS = L; BIST failure
PASS = H; LOCK = H before BIST can be enabled, then 1x10-9 error rate achieved across link.
LVDS SERIAL INTERFACE PINS
53 RIN+ LVDS_I Receiver LVDS True (+) Input — This input is intended to be terminated with a 100Ω load to the RIN+ pin. The interconnect must be AC Coupled to this pin with a 100nF capacitor.
54 RIN− LVDS_I Receiver LVDS Inverted (−) Input — This input is intended to be terminated with a 100Ω load to the RIN- pin. The interconnect must be AC Coupled to this pin with a 100nF capacitor.
POWER / GROUND PINS
51 VDD VDD Analog LVDS Voltage Supply, POWER
59 VDD VDD Analog Voltage Supply, PLL POWER
57 VDD VDD Analog Voltage supply, PLL VCO POWER
32 VDD VDD Digital Voltage Supply, LOGIC POWER
46 VDD VDD Digital Voltage Supply, LOGIC POWER
40 VDD VDD Digital Voltage Supply, LVCMOS Output POWER
26 VDD VDD Digital Voltage Supply, LVCMOS Output POWER
11 VDD VDD Digital Voltage Supply, LVCMOS Output POWER
52 VSS GND Analog LVDS GROUND
58 VSS GND Analog Ground, PLL GROUND
56 VSS GND Analog Ground, PLL VCO GROUND
31 VSS GND Digital Ground, Logic GROUND
47 VSS GND Digital Ground, LOGIC GROUND
39 VSS GND Digital Ground, LVCMOS Output GROUND
25 VSS GND Digital Ground, LVCMOS Output GROUND
12 VSS GND Digital Ground, LVCMOS Output GROUND