JAJSI09I September   2009  – October  2019 DS90UR905Q-Q1 , DS90UR906Q-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     DS90UR905Q-Q1 Serializer Pin Functions
    2.     DS90UR906Q-Q1 Deserializer Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Serializer DC Electrical Characteristics
    6. 7.6  Deserializer DC Electrical Characteristics
    7. 7.7  DC and AC Serial Control Bus Characteristics
    8. 7.8  Timing Requirements for DC and AC Serial Control Bus
    9. 7.9  Timing Requirements for Serializer PCLK
    10. 7.10 Timing Requirements for Serial Control Bus
    11. 7.11 Switching Characteristics: Serializer
    12. 7.12 Switching Characteristics: Deserializer
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Data Transfer
      2. 8.3.2 Video Control Signal Filter — Serializer and Deserializer
      3. 8.3.3 Serializer Functional Description
        1. 8.3.3.1 EMI Reduction Features
          1. 8.3.3.1.1 Serializer Spread Spectrum Compatibility
        2. 8.3.3.2 Signal Quality Enhancers
          1. 8.3.3.2.1 Serializer VOD Select (VODSEL)
          2. 8.3.3.2.2 Serializer De-Emphasis (De-Emph)
        3. 8.3.3.3 Power-Saving Features
          1. 8.3.3.3.1 Serializer Power-down Feature (PDB)
          2. 8.3.3.3.2 Serializer Stop Clock Feature
          3. 8.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
        4. 8.3.3.4 Serializer Pixel Clock Edge Select (RFB)
        5. 8.3.3.5 Optional Serial Bus Control
        6. 8.3.3.6 Optional BIST Mode
      4. 8.3.4 Deserializer Functional Description
        1. 8.3.4.1  Signal Quality Enhancers
          1. 8.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 8.3.4.2  EMI Reduction Features
          1. 8.3.4.2.1 Deserializer Output Slew (OS_PCLK/DATA)
          2. 8.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) — Optional
          3. 8.3.4.2.3 Deserializer SSCG Generation — Optional
          4. 8.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
        3. 8.3.4.3  Power-Saving Features
          1. 8.3.4.3.1 Deserializer Power-Down Feature (PDB)
          2. 8.3.4.3.2 Deserializer Stop Stream SLEEP Feature
        4. 8.3.4.4  Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
        5. 8.3.4.5  Deserializer Oscillator Output (Optional)
        6. 8.3.4.6  Deserializer OP_LOW (Optional)
        7. 8.3.4.7  Deserializer Pixel Clock Edge Select (RFB)
        8. 8.3.4.8  Deserializer Control Signal Filter (Optional)
        9. 8.3.4.9  Deserializer Low Frequency Optimization (LF_Mode)
        10. 8.3.4.10 Deserializer Map Select
        11. 8.3.4.11 Deserializer Strap Input Pins
        12. 8.3.4.12 Optional Serial Bus Control
        13. 8.3.4.13 Optional BIST Mode
      5. 8.3.5 Built-In Self Test (BIST)
        1. 8.3.5.1 Sample BIST Sequence
        2. 8.3.5.2 BER Calculations
      6. 8.3.6 Optional Serial Bus Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serializer and Deserializer Operating Modes and Backward Compatibility (CONFIG[1:0])
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Display Application
      2. 9.1.2 Live Link Insertion
      3. 9.1.3 Alternate Color / Data Mapping
    2. 9.2 Typical Applications
      1. 9.2.1 DS90UR905Q-Q1 Typical Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 DS90UR906Q-Q1 Typical Connection
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Transmission Media
      2. 11.1.2 LVDS Interconnect Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 改訂履歴

Changes from H Revision (July 2015) to I Revision

  • Fixed typo in power down supply current units - changed mA to uA Go

Changes from G Revision (April 2013) to H Revision

  • 「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加Go

Changes from F Revision (January 2011) to G Revision

  • データシートのレイアウトをナショナル・セミコンダクター形式からTI形式に変更Go

Changes from E Revision (August 2010) to F Revision

  • Modified ESD to include IEC condition (330 Ohm, 150pF)Go
  • Updated deserializer parameters: IDD1, IDDZ, IDDIOZ, IDDR, VOH, VOL, tROS, tRDC Go
  • Updated Figure 14 and Figure 15 to reflect data measurement at VDDIO/2 Go
  • Updated Figure 38 – C13 changed to 4.7uF Go

Changes from D Revision (May 2010) to E Revision

  • 「データのランダム化とスクランブル」、「ノイズ・マージン」、「一般的な性能曲線」セクションを削除Go
  • 注文情報を変更し、NSPN の列に NOPB 割り当てを追加 (NSID 列の置き換え)Go
  • Corrected ESD Ratings to IEC 61000 – 4 – 2 from ISO 10605 (duplication). Go
  • Added RPU = 10k Ω condition for the Serial Control Bus Characteristics of tR and tF. Go

Changes from C Revision (March 2010) to D Revision

  • DS90UR906Q-Q1 data sheet limits have been updated per characterization results Go
  • Corrected register 5 from RFB to VODSEL and register 4 from VODSEL to RFB in Table 14Go

Changes from B Revision (Feburary 2010) to C Revision

  • Added reference to soldering profileGo
  • Added ESD CDM and ESD MM valuesGo
  • Updated RθA value Go

Changes from A Revision (September 2009) to B Revision

  • IDDT3 および IDDIOT3 (ランダム・パターン) を削除、制限がチェッカー・ボード・パターンと同じであるためGo
  • 特性付けの結果に合わせて DS90UR905Q データシートの制限を更新、これは最終的な制限Go
  • Updated DS90UR905Q-Q1 Typical Connection Diagram — Pin Control. Ref 30102044 Go
  • Updated DS90UR906Q-Q1 Pin Diagram: strap changes on pin11, pin14, and pin42 Go
  • Added strap to pin 11 “ OS_PCLK ” (Output Slew_PCLK) Go
  • Changed strap pin 14 feature from “ RDS ” to “ OS_DATA ” (Output Slew_DATA) Go
  • Added strap to pin 42 “ OP_LOW ” (Output LOW) Go
  • Updated DS90UR906Q-Q1 Typical Connection Diagram — Pin Control. Ref 30102045 Go
  • Updated DS90UR906Q-Q1 Deserializer Pin Descriptions: RDS feature changed to OS_PCLK and OS_DATA. Added OP_LOW feature Go
  • Created OP_LOW timing Figure 28. Ref 30102065 Go
  • Created OP_LOW timing Figure 29. Ref 30102066 Go
  • Updated Table 12: deleted ID[x] Address 7'b 110 1000 (h'68) (8'b 1101 0000 (h'D0))Go
  • Updated Table 13: deleted ID[x] Address 7'b 111 0000 (h'70) (8'b 1110 0000 (h'E0))Go
  • Changed Table 14 ADD \ 1 \ bit \ 6:0 \ ID[x]: deleted Device ID 7b'1101 00 (h'68). Only four (4) IDs will be availableGo
  • Changed Table 15: ADD \ 0 \ bit \ 6 \ OSS_SEL: “ OSS_SEL ” changed feature to “ OS_PCLK ” (Output Slew_PCLK). OSS_SEL moved to ADD \ 2 \ bit \ 6 \Go
  • Changed Table 15: ADD \ 0 \ bit \ 5 \ RDS: changed “ RDS ” feature to OS_DATA (Output Slew_DATA) Go
  • Changed Table 15: ADD \ 1\ bit \ 6:0 \ ID[x]: deleted Device ID 7b'1110 00 (h'70). Only four (4) IDs will be available. Go
  • Changed Table 15: ADD \ 2 \ bit \ 7 \ Reserved: changed “ Reserved ” to “ OP_LOW ”Go
  • Changed Table 15: ADD \ 2 \ bit \ 6 \ Reserved: changed “ Reserved ” to “ OSS_SEL ”Go