SNOSCY7 June   2014 LP2996A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Descriptions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Capacitor
      2. 8.1.2 Output Capacitor
      3. 8.1.3 Thermal Dissipation
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Circuit
      2. 8.2.2 DDR-III Applications
      3. 8.2.3 DDR-II Applications
      4. 8.2.4 SSTL-2 Applications
      5. 8.2.5 Level Shifting
        1. 8.2.5.1 Output Capacitor Selection
      6. 8.2.6 HSTL Applications
      7. 8.2.7 QDR Applications
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
    4. 10.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 11Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

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Pin Functions

PIN TYPE DESCRIPTION
1 GND Ground
2 SD Shutdown
3 VSENSE Feedback pin for regulating VTT.
4 VREF Buffered internal reference voltage of VDDQ/2
5 VDDQ Input for internal reference equal to VDDQ/2
6 AVIN Analog input pin
7 PVIN Power input pin
8 VTT Output voltage for connection to termination resistors
EP Exposed pad thermal connection. Connect to Ground.

5.1 Pin Descriptions

AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2996A. AVIN is used to supply all the internal control circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages close to VTT. The disadvantage of high values of PVIN is that the internal power loss will also increase, thermally limiting the design. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This eliminates the need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3 V to prevent the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where VTT is tri-stated and VREF remains active.
VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50 kΩ resistors. This ensures that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5 V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5 V signal, which will create a 1.25 V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT over temperature).

VSENSE

The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the LP2996A then the long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load regulation is not used then the VSENSE pin must still be connected to VTT. Care should be taken when a long VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small 0.1 uF ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors.
SHUTDOWN The LP2996A contains an active low shutdown pin that can be used to tri-state VTT. During shutdown VTT should not be exposed to voltages that exceed AVIN. With the shutdown pin asserted low the quiescent current of the LP2996A will drop, however, VDDQ will always maintain its constant impedance of 100 kΩ for generating the internal reference. Therefore to calculate the total power loss in shutdown both currents need to be considered. For more information refer to the Thermal Dissipation section. The shutdown pin also has an internal pull-up current, therefore to turn the part on the shutdown pin can either be connected to AVIN or left open.
VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state and thermal shutdown events for the suspend to RAM functionality.
VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ / 2. The LP2996A is designed to handle peak transient currents of up to ± 3 A with a fast transient response. The maximum continuous current is a function of VIN and can be viewed in the Typical Performance Characteristics section. If a transient is expected to last above the maximum continuous current rating for a significant amount of time then the output capacitor should be sized large enough to prevent an excessive voltage drop. Despite the fact that the LP2996A is designed to handle large transient output currents it is not capable of handling these for long durations, under all conditions. The reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal power loss. If large currents are required for longer durations, then care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal derating should always be used (please refer to the Thermal Dissipation section). If the junction temperature exceeds the thermal shutdown point than VTT will tri-state until the part returns below the hysteretic trip-point.