JAJSG88D May   2013  – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
    8. 8.8  Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
    9. 8.9  Inputs – Interrupts DVCC Domain Port P6 (P6.0 to P6.7)
    10. 8.10 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    11. 8.11 Leakage Current – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 8.12 Leakage Current – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    13. 8.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    14. 8.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    15. 8.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    16. 8.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    17. 8.17 Output Frequency – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    18. 8.18 Output Frequency – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    19. 8.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    20. 8.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    21. 8.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 8.22 Crystal Oscillator, XT2
    23. 8.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 8.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 8.25 DCO Frequency
    26. 8.26 PMM, Brownout Reset (BOR)
    27. 8.27 PMM, Core Voltage
    28. 8.28 PMM, SVS High Side
    29. 8.29 PMM, SVM High Side
    30. 8.30 PMM, SVS Low Side
    31. 8.31 PMM, SVM Low Side
    32. 8.32 Wake-up Times From Low-Power Modes and Reset
    33. 8.33 Timer_A
    34. 8.34 Timer_B
    35. 8.35 USCI (UART Mode) Clock Frequency
    36. 8.36 USCI (UART Mode)
    37. 8.37 USCI (SPI Master Mode) Clock Frequency
    38. 8.38 USCI (SPI Master Mode)
    39. 8.39 USCI (SPI Slave Mode)
    40. 8.40 USCI (I2C Mode)
    41. 8.41 10-Bit ADC, Power Supply and Input Range Conditions
    42. 8.42 10-Bit ADC, Timing Parameters
    43. 8.43 10-Bit ADC, Linearity Parameters
    44. 8.44 REF, External Reference
    45. 8.45 REF, Built-In Reference
    46. 8.46 Comparator_B
    47. 8.47 Flash Memory
    48. 8.48 JTAG and Spy-Bi-Wire Interface
    49. 8.49 DVIO BSL Entry
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
      1. 9.5.1 Bootloader – I2C
      2. 9.5.2 Bootloader – UART
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Port Mapping Controller
      3. 9.9.3  Oscillator and System Clock
      4. 9.9.4  Power-Management Module (PMM)
      5. 9.9.5  Hardware Multiplier
      6. 9.9.6  Real-Time Clock (RTC_A)
      7. 9.9.7  Watchdog Timer (WDT_A)
      8. 9.9.8  System Module (SYS)
      9. 9.9.9  DMA Controller
      10. 9.9.10 Universal Serial Communication Interface (USCI)
      11. 9.9.11 TA0
      12. 9.9.12 TA1
      13. 9.9.13 TA2
      14. 9.9.14 TB0
      15. 9.9.15 Comparator_B
      16. 9.9.16 ADC10_A
      17. 9.9.17 CRC16
      18. 9.9.18 Reference (REF) Module Voltage Reference
      19. 9.9.19 Embedded Emulation Module (EEM) (S Version)
      20. 9.9.20 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
      10. 9.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 9.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  サポート・リソース
    7. 10.7  Trademarks
    8. 10.8  静電気放電に関する注意事項
    9. 10.9  Export Control Notice
    10. 10.10 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Revision History

Changes from revision C to revision D

Changes from September 28, 2018 to October 20, 2020

  • 文書全体にわたってセクション、表、図、相互参照の採番方法を更新Go
  • 文書全体にわたって nFBGA パッケージ (ZXH) の情報を追加Go
  • 「表 3-1」の ZQE パッケージの注文可能なすべての部品番号のステータスの変更に関する注を追加Go
  • Corrected the description of the P2.3/UCB3SOMI/UCB3SCL signals in Table 7-1, Terminal Functions Go
  • Changed the MAX value of the IERASE and IMERASE, IBANK parameters in Section 8.47, Flash Memory Go

Changes from revision B to revision C

Changes from November 26, 2015 to September 27, 2018

  • Added Section 6.1, Related Products Go
  • Added color to P1.0 (pin H2) and DVSS (pin F9) to indicate supply from DVIO in Figure 7-2, 80-Pin ZXH or ZQE Package (Top View) Go
  • Added typical conditions statements at the beginning of Section 8, Specifications Go
  • Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 8.26, PMM, Brownout Reset (BOR) Go
  • Updated notes (1) and (2) and added note (3) in Section 8.32, Wake-up Times From Low-Power Modes and Reset Go
  • Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Section 8.42, 10-Bit ADC, Timing Parameters, because ADC10CLK is after divisionGo
  • Added second row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in Section 8.46, Comparator_B Go
  • Renamed FCTL4.MGR0 and MGR1 bits in the fMCLK,MGR parameter in Section 8.47, Flash Memory, to be consistent with header files Go
  • Added links to the custom BSL430 package download in Section 9.5, Bootloader (BSL) Go
  • Replaced former section Development Tools Support with Section 10.3, Tools and Software Go
  • Updated list of related documentation in Section 10.4, Documentation Support Go

Changes from revision A to revision B

Changes from July 31, 2013 to November 25, 2015

  • 全体を通してドキュメントのフォーマットと編成を変更、セクションの番号追加も含むGo
  • 「製品情報」表を追加Go
  • Moved Section 4, Functional Block Diagram Go
  • Added 16KB RAM option in Figure 4-1, Functional Block Diagram Go
  • Added Section 6, Device Comparison, and moved Table 6-1 to itGo
  • Added Section 7, Terminal Configuration and Functions, and moved pinout drawings and terminal functions table to it Go
  • Added indication of terminals powered by DVIO in RGC pinout Go
  • Added indication of terminals powered by DVIO in ZQE pinoutGo
  • Removed preview YFF pinoutGo
  • Added SUPPLY column and removed YFF column in Table 7-1, Terminal Functions Go
  • Added Section 8.2, ESD Ratings Go
  • Added note on CVCORE Go
  • Added Section 8.6, Thermal Resistance Characteristics Go
  • Moved note on RPull from Section 8.7 to Section 8.8 Go
  • Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF in Section 8.21, Crystal Oscillator, XT1, Low-Frequency Mode Go
  • Corrected Test Conditions (removed VREF–) for all parameters in Section 8.43 Go
  • Updated Test Conditions for all parameters in Section 8.43, 10-Bit ADC, Linearity Parameters: changed from "CVREF+ = 20 pF" to "CVeREF+ = 20 pF"; changed from "(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to "1.4 V ≤ (VeREF+ – VeREF–)"Go
  • Added "CVeREF+ = 20 pF" to EI Test ConditionsGo
  • Added "ADC10SREFx = 11b" to Test Conditions for EG and ET Go
  • Corrected Test Conditions (removed VREF–) for VeREF+, VeREF–, and (VeREF+ – VeREF–) parameters in Section 8.44, REF, External Reference Go
  • Changed MIN value of AVCC(min) with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V in Section 8.45, REF, Built-In Reference Go
  • Corrected spelling of MRG bits in fMCLK,MRG parameter symbol and descriptionGo
  • Throughout document, changed all instances of "bootstrap loader" to "bootloader"Go
  • Added note to clarify that all JTAG pins are on DVCCGo
  • Added note to indicate that all SBW pins are on DVCCGo
  • Corrected spelling of NMIIFG in Table 9-10, System Module Interrupt Vector Registers Go
  • Removed YFF package information from Table 9-12, TA0 Signal Connections Go
  • Removed YFF package information from Table 9-13, TA1 Signal Connections Go
  • Removed YFF package information from Table 9-14, TA2 Signal Connections Go
  • Removed YFF package information from Table 9-15, TB0 Signal Connections Go
  • Changed Figure 9-8, Port P5 (P5.3) Diagram (added P5SEL.2 and XT2BYPASS inputs with AND and OR gates) Go
  • Changed P5SEL.3 column from X to 0 for "P5.3 (I/O)" rowsGo
  • Changed Figure 9-10, Port P5 (P5.5) Diagram (added P5SEL.5 input and OR gate)Go
  • Changed P5SEL.5 column from X to 0 for "P5.5 (I/O)" rowsGo
  • Added Section 10 and moved Development Tools Support, Device and Development Tool Nomenclature, Trademarks, and Electrostatic Discharge Caution sections to itGo
  • Added Section 11, Mechanical, Packaging, and Orderable Information Go

Changes from initial release to revision A

REVISION CHANGES
SLAS903A July 2013

Updated PRODUCT PREVIEW release.

Added Section 1.

Changed Section 1.

Added Development Tools Support and Section 1.
SLAS903 July 2013 PRODUCT PREVIEW release

Changes from Revision () to Revision ()