JAJSGC0F September   2009  – October 2018 TPS386000 , TPS386040

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      TPS386000代表的アプリケーション回路： FPGA電源の監視
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Monitoring
      2. 8.3.2 Manual Reset
      3. 8.3.3 Watchdog Timer
      4. 8.3.4 Reset Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Detection
      2. 9.1.2 Undervoltage and Overvoltage Detection
      3. 9.1.3 Sensing a Negative Voltage
      4. 9.1.4 Reset Delay Time
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価モジュール
        2. 12.1.1.2 SPICEモデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGP Package
20-Pin VQFN
Top View
TPS386000 TPS386040 po_000_040_bvs105.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VDD 14 I Supply voltage. TI recommends connecting a 0.1-μF ceramic capacitor close to this pin.
GND 12 — Ground
SENSE1 10 I Monitor voltage input to SVS-1 When the voltage at this terminal drops below the threshold voltage (VITN), RESET1 is asserted.
SENSE2 9 I Monitor voltage input to SVS-2 When the voltage at this terminal drops below the threshold voltage (VITN), RESET2 is asserted.
SENSE3 8 I Monitor voltage input to SVS-3 When the voltage at this terminal drops below the threshold voltage (VITN), RESET3 is asserted.
SENSE4L 7 I Falling monitor voltage input to SVS-4. When the voltage at this terminal drops below the threshold voltage (VITN), RESET4 is asserted.
SENSE4H 6 I Rising monitor voltage input to SVS-4. When the voltage at this terminal exceeds the threshold voltage (VITP), RESET4 is asserted. This pin can also be used to monitor the negative voltage rail in combination with VREF pin. Connect to GND if not being used.
CT1 5 — Reset delay programming pin for SVS-1 Connecting this pin to VDD through a 40-kΩ to
200-kΩ resistor, or leaving it open, selects a fixed delay time (see the Electrical Characteristics). Connecting a capacitor > 220 pF between this pin and GND selects the programmable delay time (see the Reset Delay Time section).
CT2 4 — Reset delay programming pin for SVS-2
CT3 3 — Reset delay programming pin for SVS-3
CT4 2 — Reset delay programming pin for SVS-4
VREF 13 O Reference voltage output. By connecting a resistor network between this pin and the negative power rail, SENSE4H can monitor the negative power rail. This pin is intended to only source current into resistor(s). Do not connect resistor(s) to a voltage higher than 1.2 V. Do not connect only a capacitor.
MR 1 I Manual reset input for SVS-1. Logic low level of this pin asserts RESET1.
WDI 20 I Watchdog timer (WDT) trigger input. Inputting either a positive or negative logic edge every
610 ms (typical) prevents WDT time out at the WDO or WDO pin. Timer starts from releasing event of RESET1.
NC 11 — Not internal connection. TI recommends connecting this pin to the GND pin (pin 12), which is next to this pin.
Thermal Pad PAD — This pad is the IC substrate. This pad must be connected only to GND or to the floating thermal pattern on the printed-circuit board (PCB).
TPS386000
RESET1 15 O Active low reset output of SVS-1 RESETn is an open-drain output pin. When RESETn is asserted, this pin remains in a low-impedance state. When RESETn is released, this pin goes to a high-impedance state after the delay time programmed by CTn. A pullup resistor to VDD or another voltage source is required.
RESET2 16 O Active low reset output of SVS-2
RESET3 17 O Active low reset output of SVS-3
RESET4 18 O Active low reset output of SVS-4
WDO 19 O Watchdog timer output. This is an open-drain output pin. When WDT times out, this pin goes to a low-impedance state to GND. If there is no WDT time-out, this pin stays in a high-impedance state.
TPS386040
RESET1 15 O Active low reset output of SVS-1 RESETn is a push-pull logic buffer output pin. When RESETn is asserted, this pin remains logic low. When RESETn is released, this pin goes to logic high after the delay time programmed by CTn.
RESET2 16 O Active low reset output of SVS-2
RESET3 17 O Active low reset output of SVS-3
RESET4 18 O Active low reset output of SVS-4
WDO 19 O Watchdog timer output. This is a push-pull output pin. When WDT times out, this pin goes to logic low. If there is no WDT time-out, this pin stays in logic high.