JAJS463D NOVEMBER   2009  – March 2018 TPS40303 , TPS40304 , TPS40305

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Reference
      2. 7.3.2 Enable Functionality, Start-Up Sequence and Timing
      3. 7.3.3 Soft-Start Time
      4. 7.3.4 Oscillator and Frequency Spread Spectrum (FSS)
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Drivers
      7. 7.3.7 Prebias Start-Up
      8. 7.3.8 Power Good
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 UVLO
        2. 7.4.1.2 Disable
        3. 7.4.1.3 Calibration
        4. 7.4.1.4 Converting
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Using the TPS40305 for a 12-V to 1.8-V Point-of-Load Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Inductor Selection (L1)
          4. 8.2.1.2.4  Output Capacitor Selection (C12)
          5. 8.2.1.2.5  Peak Current Rating of Inductor
          6. 8.2.1.2.6  Input Capacitor Selection (C8)
          7. 8.2.1.2.7  MOSFET Switch Selection (Q1 and Q2)
          8. 8.2.1.2.8  Bootstrap Capacitor (C6)
          9. 8.2.1.2.9  VDD Bypass Capacitor (C7)
          10. 8.2.1.2.10 BP Bypass Capacitor (C5)
          11. 8.2.1.2.11 Short-Circuit Protection (R11)
          12. 8.2.1.2.12 Feedback Divider (R4, R5)
          13. 8.2.1.2.13 Compensation: (C2, C3, C4, R3, R6)
        3. 8.2.1.3 Application Curves
      2. 8.2.2 A High-Current, Low-Voltage Design Using the TPS40304
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Selecting the Switching Frequency
          2. 8.2.2.2.2  Inductor Selection (L1)
          3. 8.2.2.2.3  Output Capacitor Selection (C12)
          4. 8.2.2.2.4  Peak Current Rating of Inductor
          5. 8.2.2.2.5  Input Capacitor Selection (C8)
          6. 8.2.2.2.6  MOSFET Switch Selection (Q1 and Q2)
          7. 8.2.2.2.7  Bootstrap Capacitor (C6)
          8. 8.2.2.2.8  VDD Bypass Capacitor (C7)
          9. 8.2.2.2.9  BP Bypass Capacitor (C5)
          10. 8.2.2.2.10 Short-Circuit Protection (R11)
          11. 8.2.2.2.11 Feedback Divider (R4, R5)
          12. 8.2.2.2.12 Compensation: (C2, C3, C4, R3, R6)
        3. 8.2.2.3 Application Curves
      3. 8.2.3 A Synchronous Buck Application Using the TPS40303
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1  Selecting the Switching Frequency
          2. 8.2.3.2.2  Inductor Selection (L1)
          3. 8.2.3.2.3  Output Capacitor Selection (C12)
          4. 8.2.3.2.4  Peak Current Rating of Inductor
          5. 8.2.3.2.5  Input Capacitor Selection (C8)
          6. 8.2.3.2.6  MOSFET Switch Selection (Q1 and Q2)
          7. 8.2.3.2.7  Bootstrap Capacitor (C6)
          8. 8.2.3.2.8  VDD Bypass Capacitor (C7)
          9. 8.2.3.2.9  BP Bypass Capacitor (C5)
          10. 8.2.3.2.10 Short-Circuit Protection (R11)
          11. 8.2.3.2.11 Feedback Divider (R4, R5)
          12. 8.2.3.2.12 Compensation: (C2, C3, C4, R3, R6)
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 WEBENCH®ツールによるカスタム設計
    3. 11.3 ドキュメントのサポート
      1. 11.3.1 関連資料
    4. 11.4 関連リンク
    5. 11.5 ドキュメントの更新通知を受け取る方法
    6. 11.6 コミュニティ・リソース
    7. 11.7 商標
    8. 11.8 静電気放電に関する注意事項
    9. 11.9 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.2.6 Input Capacitor Selection (C8)

The input voltage ripple is divided between capacitance and ESR. For this design VRIPPLE(cap) = 150 mV and VRIPPLE(esr) = 150 mV. The minimum capacitance and maximum ESR are estimated by Equation 11.

Equation 11. TPS40303 TPS40304 TPS40305 deqcinmin_lus964.gif
Equation 12. TPS40303 TPS40304 TPS40305 deq_esrmax2_lus964.gif

The RMS current in the input capacitors is estimated by Equation 13.

Equation 13. TPS40303 TPS40304 TPS40305 deq_irmscin_lus964.gif

Two 1210, 10-µF, 25-V, X5R ceramic capacitors with approximately 2-mΩ of ESR and a 2.5-A RMS current rating each are selected. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to ensure the capacitors allow sufficient capacitance at the working voltage.