JAJS463D NOVEMBER   2009  – March 2018 TPS40303 , TPS40304 , TPS40305

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Reference
      2. 7.3.2 Enable Functionality, Start-Up Sequence and Timing
      3. 7.3.3 Soft-Start Time
      4. 7.3.4 Oscillator and Frequency Spread Spectrum (FSS)
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Drivers
      7. 7.3.7 Prebias Start-Up
      8. 7.3.8 Power Good
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 UVLO
        2. 7.4.1.2 Disable
        3. 7.4.1.3 Calibration
        4. 7.4.1.4 Converting
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Using the TPS40305 for a 12-V to 1.8-V Point-of-Load Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Inductor Selection (L1)
          4. 8.2.1.2.4  Output Capacitor Selection (C12)
          5. 8.2.1.2.5  Peak Current Rating of Inductor
          6. 8.2.1.2.6  Input Capacitor Selection (C8)
          7. 8.2.1.2.7  MOSFET Switch Selection (Q1 and Q2)
          8. 8.2.1.2.8  Bootstrap Capacitor (C6)
          9. 8.2.1.2.9  VDD Bypass Capacitor (C7)
          10. 8.2.1.2.10 BP Bypass Capacitor (C5)
          11. 8.2.1.2.11 Short-Circuit Protection (R11)
          12. 8.2.1.2.12 Feedback Divider (R4, R5)
          13. 8.2.1.2.13 Compensation: (C2, C3, C4, R3, R6)
        3. 8.2.1.3 Application Curves
      2. 8.2.2 A High-Current, Low-Voltage Design Using the TPS40304
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Selecting the Switching Frequency
          2. 8.2.2.2.2  Inductor Selection (L1)
          3. 8.2.2.2.3  Output Capacitor Selection (C12)
          4. 8.2.2.2.4  Peak Current Rating of Inductor
          5. 8.2.2.2.5  Input Capacitor Selection (C8)
          6. 8.2.2.2.6  MOSFET Switch Selection (Q1 and Q2)
          7. 8.2.2.2.7  Bootstrap Capacitor (C6)
          8. 8.2.2.2.8  VDD Bypass Capacitor (C7)
          9. 8.2.2.2.9  BP Bypass Capacitor (C5)
          10. 8.2.2.2.10 Short-Circuit Protection (R11)
          11. 8.2.2.2.11 Feedback Divider (R4, R5)
          12. 8.2.2.2.12 Compensation: (C2, C3, C4, R3, R6)
        3. 8.2.2.3 Application Curves
      3. 8.2.3 A Synchronous Buck Application Using the TPS40303
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1  Selecting the Switching Frequency
          2. 8.2.3.2.2  Inductor Selection (L1)
          3. 8.2.3.2.3  Output Capacitor Selection (C12)
          4. 8.2.3.2.4  Peak Current Rating of Inductor
          5. 8.2.3.2.5  Input Capacitor Selection (C8)
          6. 8.2.3.2.6  MOSFET Switch Selection (Q1 and Q2)
          7. 8.2.3.2.7  Bootstrap Capacitor (C6)
          8. 8.2.3.2.8  VDD Bypass Capacitor (C7)
          9. 8.2.3.2.9  BP Bypass Capacitor (C5)
          10. 8.2.3.2.10 Short-Circuit Protection (R11)
          11. 8.2.3.2.11 Feedback Divider (R4, R5)
          12. 8.2.3.2.12 Compensation: (C2, C3, C4, R3, R6)
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 WEBENCH®ツールによるカスタム設計
    3. 11.3 ドキュメントのサポート
      1. 11.3.1 関連資料
    4. 11.4 関連リンク
    5. 11.5 ドキュメントの更新通知を受け取る方法
    6. 11.6 コミュニティ・リソース
    7. 11.7 商標
    8. 11.8 静電気放電に関する注意事項
    9. 11.9 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TJ = –40°C to 125°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE REFERENCE
VFB FB input voltage TJ = 25°C, 3 V < VVDD< 20 V 597 600 603 mV
–40°C < TJ< 125°C, 3 V < VVDD< 20 V 594 600 606
INPUT SUPPLY
VVDD Input supply voltage range 3 20 V
IDDSD Shutdown supply current VEN/SS< 0.2 V 70 100 µA
IDDQ Quiescent, nonswitching Let EN/SS float, VFB = 1 V 2.5 3.5 mA
ENABLE/SOFT START
VIH High-level input voltage, EN/SS 0.55 0.7 1 V
VIL Low-level input voltage, EN/SS 0.27 0.3 0.33 V
ISS Soft-start source current 8 10 12 µA
VSS Soft-start voltage level 0.4 0.8 1.3 V
BP REGULATOR
VBP Output voltage IBP = 10 mA 6.2 6.5 6.8 V
VDO Regulator dropout voltage, VVDD – VBP IBP = 25 mA, VVDD = 3 V 70 110 mV
OSCILLATOR
fSW PWM frequency TPS40303 3 V < VVDD< 20 V 270 300 330 kHz
TPS40304 540 600 660 kHz
TPS40305 1.02 1.20 1.38 MHz
VRAMP(1) Ramp amplitude VVDD/6.6 VVDD/6 VVDD/5.4 V
fSWFSS Frequency spread-spectrum frequency deviation 12% fSW
fMOD Modulation frequency 25 kHz
PWM
DMAX(1) Maximum duty cycle TPS40303 VFB = 0 V, 3 V < VVDD< 20 V 90%
TPS40304 90%
TPS40305 85%
tON(min)(1) Minimum controllable pulse width 70 ns
tDEAD Output driver dead time HDRV off to LDRV on 5 25 35 ns
LDRV off to HDRV on 5 25 30
ERROR AMPLIFIER
GBWP(1) Gain bandwidth product 10 24 MHz
AOL(1) Open loop gain 60 dB
IIB Input bias current (current out of FB pin) VFB = 0.6 V 75 nA
IEAOP Output source current VFB = 0 V 2 mA
IEAOM Output sink current VFB = 1 V 2
PGOOD
VOV Feedback upper voltage limit for PGOOD 655 675 700 mV
VUV Feedback lower voltage limit for PGOOD 500 525 550
VPGD-HYST PGOOD hysteresis voltage at FB 25 40
RPGD PGOOD pulldown resistance VFB = 0 V, IFB = 5 mA 30 70 Ω
IPGDLK PGOOD leakage current 550 mV < VFB< 655 mV,
VPGOOD = 5 V		 10 20 µA
OUTPUT DRIVERS
RHDHI High-side driver pullup resistance VBOOT – VSW = 5 V, IHDRV = –100 mA 0.8 1.5 2.5 Ω
RHDLO High-side driver pulldown resistance VBOOT – VSW = 5 V, IHDRV = 100 mA 0.5 1 2.2 Ω
RLDHI Low-side driver pullup resistance ILDRV = –100 mA 0.8 1.5 2.5 Ω
RLDLO Low-side driver pulldown resistance ILDRV = 100 mA 0.35 0.6 1.2 Ω
tHRISE(1) High-side driver rise time CLOAD = 5 nF 15 ns
tHFALL(1) High-side driver fall time 12 ns
tLRISE(1) Low-side driver rise time 15 ns
tLFALL(1) Low-side driver fall time 10 ns
OVERCURRENT PROTECTION
tPSSC(min)(1) Minimum pulse time during short circuit 250 ns
tBLNKH(1) Switch leading-edge blanking pulse time 150 ns
VOCH OC threshold for high-side FET TJ = 25°C 360 450 580 mV
IOCSET OCSET current source TJ = 25°C 9.5 10 10.5 µA
VLD-CLAMP Maximum clamp voltage at LDRV 260 340 400 mV
VOCLOS OC comparator offset voltage for low-side FET TJ = 25°C –8 8 mV
VOCLPRO(1) Programmable OC range for low-side FET TJ = 25°C 12 300 mV
VTHTC(1) OC threshold temperature coefficient (both high-side and low-side) 3000 ppm
tOFF OC retry cycles on EN/SS pin 4 Cycle
BOOT DIODE
VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.8 V
THERMAL SHUTDOWN
TJSD(1) Junction shutdown temperature 145 °C
TJSDH(1) Hysteresis 20 °C
(1) Ensured by design. Not production tested.