JAJSE62A November   2017  – December 2021 TPS55160-Q1 , TPS55162-Q1 , TPS55165-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics — External Components
    6. 7.6  Electrical Characteristics — Supply Voltage (VINP, VINL pins)
    7. 7.7  Electrical Characteristics — Reference Voltage (VOS_FB Pin) and Output Voltage (VOUT Pin)
    8. 7.8  Electrical Characteristics — Buck-Boost
    9. 7.9  Electrical Characteristics — Undervoltage and Overvoltage Lockout
    10. 7.10 Electrical Characteristics — IGN Wakeup
    11. 7.11 Electrical Characteristics — Logic Pins PS, IGN_PWRL, SS_EN
    12. 7.12 Electrical Characteristics – Overtemperature Protection
    13. 7.13 Electrical Characteristics – Power Good
    14. 7.14 Switching Characteristics — Reference Voltage (VOS_FB Pin) and Output Voltage (VOUT Pin)
    15. 7.15 Switching Characteristics — Buck-Boost
    16. 7.16 Switching Characteristics — Undervoltage and Overvoltage Lockout
    17. 7.17 Switching Characteristics — IGN Wakeup
    18. 7.18 Switching Characteristics — Logic Pins PS, IGN_PWRL, SS_EN
    19. 7.19 Switching Characteristics – Power Good
    20. 7.20 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Spread-Spectrum Feature
      2. 8.3.2 Overcurrent Protection
      3. 8.3.3 Overtemperature Protection
      4. 8.3.4 Undervoltage Lockout and Minimum Start-Up Voltage
      5. 8.3.5 Overvoltage Lockout
      6. 8.3.6 VOUT Overvoltage Protection
      7. 8.3.7 Power-Good Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 Modes of Operation
        1. 8.4.2.1 Normal Mode
        2. 8.4.2.2 Low-Power Mode
      3. 8.4.3 Power-Up and Power-Down Sequences
      4. 8.4.4 Soft-Start Feature
      5. 8.4.5 Pulldown Resistor on VOUT
      6. 8.4.6 Output Voltage Selection
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Circuits for Output Voltage Configurations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power-Circuit Selections: CIN, L, COUT
          1. 9.2.2.1.1 Inductor Current in Step-Down Mode
          2. 9.2.2.1.2 Inductor Current in Step-Up Mode
          3. 9.2.2.1.3 Inductor Current in Buck-Boost Overlap Mode
          4. 9.2.2.1.4 Inductor Peak Current
        2. 9.2.2.2 Control-Circuit Selections
          1. 9.2.2.2.1 Bootstrap Capacitors
          2. 9.2.2.2.2 VOUT-Sense Bypass Capacitor
          3. 9.2.2.2.3 VREG Bypass Capacitor
          4. 9.2.2.2.4 PG Pullup Resistor and Delay Time
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

Figure 6-1 PWP PowerPAD™ Package20-Pin HTSSOP With Exposed Thermal PadTop View
Table 6-1 Pin Functions
PIN I/O(1) TYPE(2) DESCRIPTION
NAME NO.
PGND 1 — G Power-ground pin
L1 2 I A Buck power-stage switch node. Connect an inductor with a nominal value of 4.7 µH between the L1 and L2 pins.
BST1 3 I A Bootstrap node for the buck power stage. Connect a 100-nF capacitor between this pin and the L1 pin.
VINP 4 — P Supply-power input voltage. Connect this pin to the input supply line.
VINL 5 — P Supply-input voltage for internal biasing. Connect this pin to the input supply line.
IGN 6 I D Ignition-enable input signal. The ignition is enabled when this pin is high (1) and is disabled when this pin is low (0).
PS 7 I D Logic-level input signal to enable and disable low-power mode. The power mode is low-power mode when this pin is high (1) and is normal mode when this pin is low (1).
IGN_PWRL 8 I D Logic-level IGN power-latch signal. The IGN pin is latched when this pin is high (1) and is not latched when this pin is low (0).
SS_EN 9 I D Configuration pin to enable and disable the spread-Spectrum. The spread-spectrum feature is enabled when this pin is open and disabled when this pin is low.
PG_DLY 10 I A Configuration pin for power-good delay time. Connect this pin to a resistor with a value from 10kΩ to 100kΩ to configure the PG delay time from 0.5 ms to 40 ms. Connect this pin to ground for the default PG delay time which is 2 ms (typical).
VREG_Q(3) 11 I A Quiet feedback pin for the gate-drive supply of the buck-boost power stages. This pin must be connected close to the top side of the 4.7-µF (typical) decoupling capacitor at the VREG output pin.
VREG 12 O A Gate-drive supply for the buck-boost power stages. Apply a 4.7-µF (typical) decoupling capacitor at this pin to the power ground. The VREG pin cannot drive external loads in the application.
GND 13 — G Analog ground
VOS_FB 14 I A For the TPS55160-Q1 and TPS55162-Q1 devices, this pin is used to adjust the VOUT configuration. Connect this pin to a resistive feedback network with less than 1-MΩ total resistance between the VOUT pin, FB pin, and GND pin (analog ground).
For the TPS55165-Q1 device, this pin is used to select the output voltage. The output voltage is set to 5 V when this pin is connected to the GND pin. The output voltage is 12 V when this pin is connected to the VREG pin.
PG 15 O D Output power good pin. This pin is an open-drain pin. The status of the power-good output is good when this pin is high (1) and has a failure when this pin is low (0)
VOUT_SENSE 16 I A Sense pin for the buck-boost converter output voltage. This pin must be connected to the VOUT pin.
VOUT 17 O A Buck-boost converter output voltage
GND 18 — G Analog ground
BST2 19 I A Bootstrap node for the boost power-stage. Connect a typical 100-nF capacitor between this pin and the L2 pin.
L2 20 I A Boost power-stage switch node. Connect an inductor with a nominal value of 4.7 µH between the L1 and L2 pins.
PowerPAD — — The thermal pad must be soldered to the power ground to achieve the appropriate power dissipation through the analog ground plane.
(1) I = Input Pin, O = Output Pin
(2) A = Analog Pin, D = Digital Pin, G = Ground Pin, P = Power Pin
(3) The VREG_Q pin must be connected to the VREG pin at all times while the device is in operation to prevent possible electrostatic overstress (EOS) damage to the device.