The power-good (PG) pin is a low-side FET open-drain output which is released as soon as the output voltage is greater than the PG undervoltage threshold (essentially the output voltage is rising) and the extension time (PG_exttime) is expired. The intended usage of this pin is to release the reset of an external MCU. Therefore, the logic-input signals (IGN_PWRL and PS) are considered to be valid only when the PG pin reaches the high level.

When the output voltage is less than the PG undervoltage threshold (essentially the output voltage is falling) for a time longer than the PG deglitch filter time, the PG pin is pulled low. When the PG pin is low, the level of the PS and IGN_PWRL pins is interpreted as low, regardless of the actual level. The device goes to the OFF state if the IGN pin is low under this condition. For more information on the behavior of the PG pin for rising and falling output voltage, see Figure 8-2 through Figure 8-6.

The PG pin is operational in low-power mode. The PG extension time can be configured by connecting the PG_DLY pin to the VREG pin, the GND pin, or through an external resistor with a value from 10 kΩ to 100 kΩ to the GND pin. The extension time is as follows for the listed configurations:

• When the PG_DLY pin is shorted to the VREG pin, the typical PG extension time is 40 ms.
• When the PG_DLY pin is connected to the GND pin, the typical PG extension time is 0.6 ms.
• When the external resistor between the PG_DLY and GND pins has a value of 10 kΩ, the typical PG extension time is 3 ms.
• When the external resistor between pin the PG_DLY and GND pins has a value of 100 kΩ, the typical PG extension time is 30 ms.