JAJSMH6F July   2021  – August 2024 TPS7H5001-SP , TPS7H5002-SP , TPS7H5003-SP , TPS7H5004-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Device Options
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: TPS7H5001-SP
    7. 7.7  Electrical Characteristics: TPS7H5002-SP
    8. 7.8  Electrical Characteristics: TPS7H5003-SP
    9. 7.9  Electrical Characteristics: TPS7H5004-SP
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and VLDO
      2. 8.3.2  Start-Up
      3. 8.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Output Voltage Programming
      7. 8.3.7  Soft Start (SS)
      8. 8.3.8  Switching Frequency and External Synchronization
        1. 8.3.8.1 Internal Oscillator Mode
        2. 8.3.8.2 External Synchronization Mode
        3. 8.3.8.3 Primary-Secondary Mode
      9. 8.3.9  Primary Switching Outputs (OUTA/OUTB)
      10. 8.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 8.3.12 Pulse Skipping
      13. 8.3.13 Duty Cycle Programmability
      14. 8.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 8.3.15 Hiccup Mode Operation (HICC)
      16. 8.3.16 External Fault Protection (FAULT)
      17. 8.3.17 Slope Compensation (RSC)
      18. 8.3.18 Frequency Compensation
      19. 8.3.19 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency
        2. 9.2.2.2  Output Voltage Programming Resistors
        3. 9.2.2.3  Dead Time
        4. 9.2.2.4  Leading Edge Blank Time
        5. 9.2.2.5  Soft-Start Capacitor
        6. 9.2.2.6  Transformer
        7. 9.2.2.7  Main Switching FETs
        8. 9.2.2.8  Synchronous Rectificier FETs
        9. 9.2.2.9  RCD Clamp
        10. 9.2.2.10 Output Inductor
        11. 9.2.2.11 Output Capacitance and Filter
        12. 9.2.2.12 Sense Resistor
        13. 9.2.2.13 Hiccup Capacitor
        14. 9.2.2.14 Frequency Compensation Components
        15. 9.2.2.15 Slope Compensation Resistor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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発注情報

8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)

While the TPS7H5003-SP has a fixed dead time (50 ns typical), the TPS7H5001-SP and TPS7H5002-SP allow for the user to program two independent dead times, TDSP and TDPS, as shown in Figure 8-13. This allows for the dead times to be optimized by the user in order to prevent shoot-though between the primary and synchronous switches while attaining the best possible converter efficiency. The dead time TDPS between primary output (OUTA/OUTB) turn-off to synchronous rectifier (SRA/SRB) turn-on, can be programmed using a resistor from PS to AVSS. Likewise, the dead time TDSP between synchronous rectifier turn-off and primary output turn-on is set using a resistor from SP to AVSS. The equation for determining the values of RPS and RSP required for a desired dead time is shown in Equation 8.

Equation 8. TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP

where:

  • DT is the desired dead time in ns
  • RPS and RSP are in kΩ

If the PS and SP pins are left floating, the dead time will be set to a minimum value of 8 ns (typical). When these pins are populated, it is recommended to use a minimum resistor value of 10 kΩ for RPS and RSP. The maximum resistor value to be used is 300 kΩ. As mentioned in Soft-Start (SS) and Synchronous Rectifier Outputs (SRA and SRB), the SR outputs will be disabled during soft start, so the dead time is observed only after this sequence is complete.

After OUTA or OUTB goes high, a leading edge blank time is implemented to remove any transient noise from the current sensing loop. While the leading edge blank time is fixed (50-ns typical) for TPS7H5003-SP, the leading edge blank time for all other devices in the TPS7H500x-SP series is programmable by placing an external resistor from LEB to AVSS. This pin cannot be left floating and a minimum resistor value of 10 kΩ is required from LEB to AVSS. The maximum resistor value that should be used is 300 kΩ. The equation for determining the value of RLEB for a desired leading edge blank time is shown in Equation 9.

Equation 9. TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP

where:

  • LEB is the desired leading edge blank time in ns
  • RLEB is in kΩ


Table 8-4 Dead Time and Leading Edge Blank Time Configurations for TPS7H500x-SP
DEVICE DEAD TIME LEADING EDGE BLANK TIME
TPS7H5001-SP Resistor programmable Resistor programmable
TPS7H5002-SP Resistor programmable Resistor programmable
TPS7H5003-SP Fixed (50-ns typical) Fixed (50-ns typical)
TPS7H5004-SP Not applicable Resistor programmable

In Figure 8-13, the dead times and leading edge blank times are shown for the switching waveforms. This figure also illustrates the minimum on-time of the device, which is comprised of the programmed blank time TLEB and an internal logic delay td. Note that the dead-time waveforms for OUTB/SRB are only applicable for TPS7H5001-SP.

TPS7H5001-SP TPS7H5002-SP TPS7H5003-SP TPS7H5004-SP Outputs Timing Waveforms Figure 8-13 Outputs Timing Waveforms