JAJSBW0G December   2012  – June 2019 UCC27531 , UCC27533 , UCC27536 , UCC27537 , UCC27538

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      負バイアスを使用しない IGBT 駆動
  4. 4 改訂履歴
    1.     概要（続き）
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 VDD Undervoltage Lockout
      2. 8.3.2 Input Stage
      3. 8.3.3 Enable Function
      4. 8.3.4 Output Stage
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Driving IGBT Without Negative Bias
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input-to-Output Configuration
          2. 9.2.1.2.2 Input Threshold Type
          3. 9.2.1.2.3 VDD Bias Supply Voltage
          4. 9.2.1.2.4 Peak Source and Sink Currents
          5. 9.2.1.2.5 Enable and Disable Function
          6. 9.2.1.2.6 Propagation Delay
          7. 9.2.1.2.7 Power Dissipation
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Driving IGBT With 13-V Negative Turn-Off BIAS
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
      3. 9.2.3 Single-Output Driver
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
      4. 9.2.4 Using UCC2753x Drivers in an Inverter
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Consideration
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 商標
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Unless otherwise noted, VDD = 18 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531/8. Typical condition specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS CURRENTS
IDDoff Start-up current (UCC25731) VDD = 7.0, IN, EN=VDD 100 200 300 μA
IN, EN = GND 100 217 300
IDDoff Start-up current (UCC27533) VDD = 7.0, IN+ = GND, IN- = VDD 100 200 300 μA
IN+ = VDD, IN- = GND 100 217 300
IDDoff Start-up current (UCC27536) VDD = 7.0, IN- = GND, EN = VDD 100 217 300 μA
IN- = VDD, EN = GND 100 217 300
IDDoff Start-up current (UCC27537) VDD =7.0, IN+, EN = VDD 100 200 300 μA
IN+, EN = GND 100 217 300
IDDoff Start-up Current (UCC27538) VDD = 7.0, IN1, IN2=VDD 100 200 300 μA
IN1, IN2=GND 100 200 300
UNDERVOLTAGE LOCKOUT (UVLO)
VON Supply start threshold 8 8.9 9.8 V
VOFF Minimum operating voltage after supply start 7.3 8.2 9.1 V
VDD_H Supply voltage hysteresis 0.7 V
INPUT (IN, IN+, IN1, IN2)
VIN_H Input signal high threshold, output high Output High, IN- = LOW, EN=HIGH, IN2 or IN1 = HIGH (other is INPUT) 1.8 2 2.2 V
VIN_L Input signal low threshold, output low Output Low, IN- = LOW, EN=HIGH, IN2 or IN1 = HIGH (other is INPUT) 0.8 1 1.2 V
VIN_HYS Input signal hysteresis 1 V
INPUT (IN-)
VIN_H Input signal high threshold, output low Output low, IN+ = HIGH, EN = High 1.7 1.9 2.1 V
VIN_L Input signal low threshold, output high Output high,, IN+ = HIGH, EN = High 0.8 1 1.2 V
VIN_HYS Input signal hysteresis 0.9 V
ENABLE (EN)
VEN_H Enable signal high threshold Output High 1.7 1.9 2.1 V
VEN_L Enable signal low threshold Output Low 0.8 1 1.2 V
VEN_HYS Enable signal hysteresis 0.9 V
OUTPUTS (OUTH/OUTL)
ISRC/SNK Source peak current (OUTH)/ sink peak current (OUTL) CLOAD = 0.22 µF, f = 1 kHz –2.5/+5 A
VOH OUTH, high voltage IOUTH = -10 mA VDD –0.2 VDD –0.12 VDD –0.07 V
VOL OUTL, low voltage IOUTL = 100 mA 0.065 0.125 V
VOL OUTL, Low Voltage UCC27536 IOUTL = 100 mA 0.13 0.23 V
ROH OUTH, pull-up resistance TA = 25°C, IOUT = –10 mA 11 12 12.5 Ω
TA = –40°C to 140°C, IOUT = –10 mA 7 12 20
ROL OUTL, pull-down resistance TA = 25°C, IOUT = 100 mA 0.45 0.65 0.85 Ω
TA = –40°C to 140°C, IOUT = 100 mA 0.3 0.65 1.25
ROL OUTL, pull-down resistance UCC27536 TA = 25°C, IOUT = 100 mA 0.9 1.3 1.7 Ω
TA = –40°C to 140°C, IOUT = 100 mA 0.6 1.3 2.3