JAJSBW0G December   2012  – June 2019 UCC27531 , UCC27533 , UCC27536 , UCC27537 , UCC27538

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      負バイアスを使用しない IGBT 駆動
  4. 4 改訂履歴
    1.     概要（続き）
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 VDD Undervoltage Lockout
      2. 8.3.2 Input Stage
      3. 8.3.3 Enable Function
      4. 8.3.4 Output Stage
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Driving IGBT Without Negative Bias
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input-to-Output Configuration
          2. 9.2.1.2.2 Input Threshold Type
          3. 9.2.1.2.3 VDD Bias Supply Voltage
          4. 9.2.1.2.4 Peak Source and Sink Currents
          5. 9.2.1.2.5 Enable and Disable Function
          6. 9.2.1.2.6 Propagation Delay
          7. 9.2.1.2.7 Power Dissipation
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Driving IGBT With 13-V Negative Turn-Off BIAS
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
      3. 9.2.3 Single-Output Driver
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
      4. 9.2.4 Using UCC2753x Drivers in an Inverter
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Consideration
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 商標
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Overview

The UCC2753x family of devices are single-channel, high-speed, gate drivers capable of effectively driving MOSFET and IGBT power switches by up to 2.5-A source and 5-A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turn-on effect. The UCC2753x device can also feature a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turn-on and turn-off resistors to the OUTH and OUTL pins, respectively, and easily control the switching slew rates.

The driver has rail-to-rail drive capability and extremely small propagation delay, typically 17 ns.

The input threshold of UCC2753x is based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of VDD supply voltage. The 1-V typical hysteresis offers excellent noise immunity.

The driver has an EN pin with fixed TTL compatible threshold. EN is internally pulled up; pulling EN low disables the driver, while leaving EN open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN, IN+, IN1, and IN2 pins.

Table 1. UCC2753x Features and Benefits

FEATURE BENEFIT
High source and sink current capability, 2.5 A and 5 A (asymmetrical). High current capability offers flexibility in employing UCC2753x device to drive a variety of power switching devices at varying speeds.
Low 17 ns (typ) propagation delay. Extremely low pulse transmission distortion.
Wide VDD operating range of 10 V to 32 V. Flexibility in system design.
Can be used in split-rail systems such as driving IGBTs with both positive and negative(relative to Emitter) supplies.
Optimal for many SiC FETs.
VDD UVLO protection. Outputs are held Low in UVLO condition, which ensures predictable, glitch-free operation at power up and power down.
High UVLO of 8.9 V typical ensures that power switch is not on in high-impedance state which could result in high power dissipation or even failures.
Outputs held low when input pin (INx) in floating condition. Safety feature, especially useful in passing abnormal condition tests during safety certification
Split output structure option (OUTH, OUTL). Allows independent optimization of turn-on and turn-off speeds using series gate resistors.
Strong sink current (5 A) and low pull-down impedance (0.65 Ω). High immunity to high dV/dt Miller turn-on events.
CMOS and TTL compatible input threshold logic with wide hysteresis. Enhanced noise immunity, while retaining compatibility with microcontroller logic level input signals (3.3 V, 5 V) optimized for digital power.
Input capable of withstanding –6.5 V. Enhanced signal reliability in noisy environments that experience ground bounce on the gate driver.