デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
UCC3813-xデバイス・ファミリは、高速で低消費電力の集積回路で、オフラインおよびDC/DC固定周波数電流モードのスイッチング電源を最小の部品数で設計するため必要な、すべての制御および駆動部品が含まれています。
これらのデバイスは、UC384xデバイス・ファミリとピン構成が同じで、内部的なフルサイクル・ソフトスタートや、電流センス入力の内部リーディングエッジ・ブランキングなどの追加機能も提供します。
UCC3813-xデバイス・ファミリは、各種のパッケージ・オプション、温度範囲オプション、最大デューティ・サイクルの選択、クリティカル電圧レベルの選択が使用可能です。UCC3813-3やUCC3813-5など基準電圧の低いデバイスは、バッテリで動作するシステムに最適です。これに対して、UCC3813-2およびUCC3813-4デバイスは基準電圧とUVLOヒステリシスが高く、オフライン電源での使用に理想的です。
UCC2813-xデバイス・シリーズは-40℃~85℃、UCC3813-xデバイス・シリーズは0℃~70℃での動作が規定されています。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
UCC2813-x、 UCC3813-x |
PDIP (8) | 6.35mm×9.81mm |
SOIC (8) | 3.91mm×4.90mm | |
TSSOP (8) | 4.40mm×3.00mm |
Changes from D Revision (May 2013) to E Revision
Changes from C Revision (August 2010) to D Revision
Changes from B Revision (April 2008) to C Revision
PART NUMBER(1) | MAXIMUM DUTY CYCLE | REFERENCE VOLTAGE | TURNON THRESHOLD | TURNOFF THRESHOLD | UNIT |
---|---|---|---|---|---|
UCCx813-0 | 100% | 5 | 7.2 | 6.9 | V |
UCCx813-1 | 50% | 5 | 9.4 | 7.4 | V |
UCCx813-2 | 100% | 5 | 12.5 | 8.3 | V |
UCCx813-3 | 100% | 4 | 4.1 | 3.6 | V |
UCCx813-4 | 50% | 5 | 12.5 | 8.3 | V |
UCCx813-5 | 50% | 4 | 4.1 | 3.6 | V |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
COMP | 1 | O | COMP is the output of the error amplifier and the input of the PWM comparator. Feedback loop compensation is applied between this pin and the FB pin. |
CS | 3 | I | CS is the input to the current-sense comparators: the PWM comparator and the overcurrent comparator. |
FB | 2 | I | FB is the inverting input of the error amplifier. |
GND | 5 | — | GND is the reference ground and power ground for all functions of this device. |
OUT | 6 | O | OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET. |
RC | 4 | I | RC is the oscillator timing programming pin. An external resistor and capacitor are applied to this input to program the switching frequency and maximum duty-cycle. |
REF | 8 | O | REF is the voltage reference for the error amplifier and many other functions, and is the bias source for logic functions of this device. |
VCC | 7 | I | VCC is the bias-power input for this device. In normal operation, VCC is connected to a voltage source through a current-limiting resistor. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC voltage(3) | 12 | V | ||
VCC current | 30 | mA | ||
OUT current | ±1 | A | ||
OUT energy (capacitive load) | 20 | µJ | ||
Analog inputs | FB, CS, RC, COMP | –0.3 | 6.3 or VVCC + 0.3(4) |
V |
Power dissipation at TA < 25°C | N package | 1 | W | |
D package | 0.65 | |||
Lead temperature, soldering (10 s) | 300 | °C | ||
Junction temperature | –55 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VVCC | VCC bias supply voltage from a low impedance source | 11 | V | ||
IVCC | Supply bias current | 25 | mA | ||
VOUT | Gate driver output voltage | –0.1 | VVCC | V | |
IOUT | Average OUT pin current | 20 | mA | ||
IREF | REF pin output current | 5 | mA | ||
Voltage on analog pins | FB, CS, RC, COMP | –0.1 | 6 or VVCC(1) | V | |
fOSC | Oscillator frequency | 1 | MHz |
THERMAL METRIC(1) | UCCx813-x | UNIT | |||
---|---|---|---|---|---|
P (PDIP) | D (SOIC) | PW (TSSOP) | |||
8 PINS | 8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 50.9 | 107.5 | 153.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 40.3 | 49.3 | 38.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 28.1 | 48.7 | 83.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 17.6 | 6.6 | 2.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 28 | 48 | 82 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
REFERENCE | ||||||
Output voltage | TJ = 25°C, I = 0.2 mA, UCCx813-[0,1,2,4] | 4.925 | 5 | 5.075 | V | |
TJ = 25°C, I = 0.2 mA, UCCx813-[3,5] | 3.94 | 4 | 4.06 | |||
Load regulation | 0.2 mA < I < 5 mA | 10 | 30 | mV | ||
Total variation | UCCx813-[0,1,2,4](5) | 4.84 | 5 | 5.1 | V | |
UCCx813-[3,5](5) | 3.84 | 4 | 4.08 | |||
Output noise voltage | 10 Hz ≤ f ≤ 10 kHz, TJ = 25°C(7) | 70 | µV | |||
Long term stability | TA = 125°C, 1000 hours(7) | 5 | mV | |||
Output short circuit | –5 | –35 | mA | |||
OSCILLATOR | ||||||
Oscillator frequency | UCCx813-[0,1,2,4](2) | 40 | 46 | 52 | kHz | |
UCCx813-[3,5](2) | 26 | 31 | 36 | |||
Temperature stability | See note (7) | 2.5% | ||||
Amplitude peak-to-peak | 2.25 | 2.4 | 2.55 | V | ||
Oscillator peak voltage | 2.45 | V | ||||
ERROR AMPLIFIER | ||||||
Input voltage | VCOMP = 2.5 V; UCCx813-[0,1,2,4] | 2.42 | 2.5 | 2.56 | V | |
VCOMP = 2 V; UCCx813-[3,5] | 1.92 | 2 | 2.05 | |||
Input bias current | –2 | 2 | µA | |||
Open loop voltage gain | 60 | 80 | dB | |||
COMP sink current | VFB = 2.7 V, VCOMP = 1.1 V | 0.4 | 2.5 | mA | ||
COMP source current | VFB = 1.8 V, VCOMP = VREF – 1.2 V | –0.2 | –0.5 | –0.8 | mA | |
Gain-bandwidth product | See note (7) | 2 | MHz | |||
PWM | ||||||
Maximum duty cycle | UCCx813-[0,2,3] | 97% | 99% | 100% | ||
UCCx813-[1,4,5] | 48% | 49% | 50% | |||
Minimum duty cycle | VCOMP = 0 V | 0% | ||||
CURRENT SENSE | ||||||
Gain | See note (3) | 1.1 | 1.65 | 1.8 | V/V | |
Maximum input signal | VCOMP = 5 V(4) | 0.9 | 1 | 1.1 | V | |
Input bias current | –200 | 200 | nA | |||
CS blank time | 50 | 100 | 150 | ns | ||
Overcurrent threshold | 1.32 | 1.55 | 1.7 | V | ||
COMP to CS offset | VCS = 0 V | 0.45 | 0.9 | 1.35 | V | |
OUTPUT | ||||||
OUT low level | I = 20 mA, all parts | 0.1 | 0.4 | V | ||
I = 200 mA, all parts | 0.35 | 0.9 | ||||
I = 50 mA, VVCC = 5 V, UCCx813-[3,5] | 0.15 | 0.4 | ||||
I = 20 mA, VCC = 0 V, all parts | 0.7 | 1.2 | ||||
VVCC – OUT | OUT high Vsat | I = –20 mA, all parts | 0.15 | 0.4 | V | |
I = –200 mA, all parts | 1 | 1.9 | ||||
I = –50 mA, VVCC = 5 V, UCCx813-[3,5] | 0.4 | 0.9 | ||||
Rise time | CL = 1 nF | 41 | 70 | ns | ||
Fall time | CL = 1 nF | 44 | 75 | ns | ||
UNDERVOLTAGE LOCKOUT | ||||||
Start threshold (6) | UCCx813-0 | 6.6 | 7.2 | 7.8 | V | |
UCCx813-1 | 8.6 | 9.4 | 10.2 | |||
UCCx813-[2,4] | 11.5 | 12.5 | 13.5 | |||
UCCx813-[3,5] | 3.7 | 4.1 | 4.5 | |||
Stop threshold (6) | UCCx813-0 | 6.3 | 6.9 | 7.5 | V | |
UCCx813-1 | 6.8 | 7.4 | 8 | |||
UCCx813-[2,4] | 7.6 | 8.3 | 9 | |||
UCCx813-[3,5] | 3.2 | 3.6 | 4 | |||
Start to stop hysteresis | UCCx813-0 | 0.12 | 0.3 | 0.48 | V | |
UCCx813-1 | 1.6 | 2 | 2.4 | |||
UCCx813-[2,4] | 3.5 | 4.2 | 5.1 | |||
UCCx813-[3,5] | 0.2 | 0.5 | 0.8 | |||
SOFT START | ||||||
COMP rise time | VFB = 1.8 V, Rise from 0.5 V to REF – 1 V | 4 | ms | |||
OVERALL | ||||||
Start-up current | VVCC < start threshold | 0.1 | 0.23 | mA | ||
Operating supply current | VFB = 0 V, VCS = 0 V, VRC = 0 V | 0.5 | 1.2 | mA | ||
VCC internal Zener voltage(6) | ICC = 10 mA | 12 | 13.5 | 15 | V | |
VCC internal Zener voltage minus start-threshold voltage (6) | UCCx813-[2,4] | 0.5 | 1 | V |
The UCCx813-x family of high-speed, low-power integrated circuits contain all of the control and drive functions required for off-line and DC-to-DC fixed-frequency current-mode switched-mode power supplies having minimal external parts count. The UCCx813-x family is a cost-reduced version of the UCCx80x family, with some relaxation of certain parameter limits. See Differences Between the UCC3813 and UCC3800 PWM Families for more information.
These devices have the same pin configuration as the UCx84x and UCx84xA families, and also offer the added features of internal full-cycle soft start and internal leading-edge blanking of the current-sense input. The UCCx813-x devices are pin-out compatible with the UCx84x and UCx84xA families, however they are not plug-in compatible. In general, the UCCx813-x requires fewer external components and consumes less operating current.
The UCCx813-x family offers numerous advantages that allow the power supply design engineer to meet their challenging requirements.
Features include:
COMP is the output of the error amplifier and the input of the PWM comparator. Unlike earlier-generation devices, the error amplifier in the UCCx813-x device family is a true low-output-impedance 2-MHz operational amplifier. As such, the COMP terminal both sources and sinks current. However, the error amplifier is internally current limited, so zero duty cycle may be commanded by externally forcing COMP to GND.
The UCCx813-x device family features built-in full cycle soft start at power up and after fault recovery, and no external components are necessary. Soft start is implemented as a rising clamp on the COMP voltage, increasing from 0 V to 5 V in 4 ms.
CS is the input to the current-sense comparators. The UCCx813-x current sense is significantly different from its predecessor. The UCCx813-x device family has two different current-sense comparators: the PWM comparator and an overcurrent comparator. The overcurrent comparator is intended only for fault sensing, and exceeding the overcurrent threshold causes a soft-start cycle. The earlier UC3842 family current-sense input connects to only the PWM comparator.
The UCCx813-x device family contains digital current-sense filtering, which disconnects the CS terminal from the current sense comparator during the 100-ns interval immediately following the rising edge of the OUT pin. This digital filtering, also called leading-edge blanking, prevents false triggering due to leading edge noises which means that in most applications, no analog filtering (external R-C filter) is required on CS. Compared to an external RC filter technique, the leading-edge blanking provides a smaller effective CS-to-OUT delay. However, the minimum non-zero on-time of the OUT signal is determined by the leading-edge-blanking time and the CS-to-OUT propagation delay. The gain of the current sense amplifier is typically 1.65 V/V in the UCCx813-x family versus typically 3 V/V in the UC3842 family. Connect CS directly to MOSFET source current sense resistor.
FB is the inverting input of the error amplifier. For best stability, keep the FB lead length as short as possible and FB stray capacitance as small as possible. At 2 MHz, the gain-bandwidth of the error amplifier is twice that of earlier UC3842 family devices, and feedback design techniques are identical.
GND is the signal reference ground and power ground for all functions on this part. TI recommends separating the signal return paths and the high current gate driver path so that signals are not affected by the switching current.
OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak currents exceeding ±750 mA (up to ±1 A). OUT is actively held low when VCC is below the UVLO threshold. This feature eliminates the need for a gate-to-source bleeder resistor associated with the MOSFET gate drive.
The high-current power driver consists of CMOS FET output devices, which can switch all of the way to GND and all of the way to VCC. The output provides very smooth rising and falling waveforms, providing very low impedances to overshoot and undershoot which means that in many cases, external Schottky clamp diodes may not be necessary on the output. Finally, no external gate voltage clamp is necessary with the UCCx813-x as the on-chip Zener diode automatically clamps the output to VCC.
RC is the oscillator timing pin. For fixed frequency operation, set the timing-capacitor charging current by connecting a resistor from REF to RC. Set frequency by connecting a timing capacitor from RC to GND. For best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions.
The UCCx813-x’s oscillator allows for operation to 1 MHz versus 500 kHz with the UC3842 family. Both devices make use of an external resistor to set the charging current for the capacitor, which determines the oscillator frequency. For the UCCx813-[0,1,2,4], use Equation 1.
where
For the UCCx813-[3,5], use Equation 2.
The recommended timing resistance is from 10 kΩ to 200 kΩ and timing capacitance is from 100 pF to 1000 pF. Never use a timing resistor less than 10 kΩ.
The two equations are different due to different reference voltages. The peak-to-peak amplitude of the oscillator waveform is 2.45 V versus 1.7 V in UC3842 family. For best performance, keep the timing capacitor lead to GND as short as possible. TI recommends separate ground traces for the timing capacitor and all other pins. The maximum duty cycle for the UCCx813-[0,2,3] is approximately 99%; the maximum duty cycle for the UCCx813-[1,4,5] is approximately 49%. The duty cycle cannot be easily modified by adjusting RT and CT, unlike the UC3842A family. The maximum duty cycle limit is set by the ratio of the external oscillator charging resistor RT and the internal oscillator discharge transistor on-resistance, like the UC3842. However, maximum duty cycle limits less than 90% (for the UCCx813-[0,2,3]) and less than 45% (for the UCCx813-[1,4,5]) can not reliably be set in this manner. For better control of maximum duty cycle, consider using the UCCx807.
REF is the voltage reference for the error amplifier and also for many other functions on the IC. REF is also used as the logic power supply for high speed switching logic on the IC. The UCCx813-[0,1,2,4] have a 5-V reference and the UCCx813-[3,5] have a 4-V reference. Both have ±1.5% accuracy at 25°C versus ±2% in the UC3842 family. The REF output short-circuit current is lower at 5 mA, compared to 30 mA in the UC3842 family.
For reference stability and to prevent noise problems with high speed switching transients, it is important to bypass REF to GND with a ceramic capacitor as close to the pins as possible. A minimum of 0.1-µF ceramic is required. Additional REF bypassing is required for external loads greater than 2.5 mA on the reference. An electrolytic capacitor can also be used in addition to the ceramic capacitor.
When VCC is greater than 1 V and less than the UVLO on-threshold, REF is internally pulled to ground through a 5-kΩ resistor which means that REF can be used as a logic output indicating power-system status.
VCC is the power input connection for this device. In normal operation, VCC is powered through a current limiting resistor to a low-impedance source. To prevent noise problems, bypass VCC to GND with a 0.1-µF ceramic capacitor in parallel as close to the VCC pin as possible. An electrolytic capacitor can also be used in addition to the ceramic capacitor.
Although quiescent VCC current is very low, total supply current is higher, depending on the OUT current. Total VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the switching frequency f and the MOSFET gate charge (Qg), average OUT current can be calculated from Equation 3.
The UCCx813-x has a lower VCC (supply voltage) clamp of 13.5 V typical versus 30 V on the UC3842. For applications that require a higher VCC voltage, a resistor must be placed in series with VCC to increase the source impedance. The maximum value of this resistor is calculated with Equation 4.
where
Additionally, the UCCx813-x has an on-chip Zener diode to limit VCC to 13.5 V, which also limits the maximum OUT voltage. If the bias-supply source is always lower than 12 V, it may be connected directly to VCC. With UVLO thresholds at 4.1 V and 3.6 V for the UCCx813-3 and UCCx813-5, respectively, 5-V PWM operation is now possible.
The UCCx813-x devices feature undervoltage lockout protection circuits for controlled operation during power-up and power-down sequences. Both the supply voltage (VVCC) and the reference voltage (VREF) are monitored by the UVLO circuitry. During UVLO, an active-low, self-biasing totem-pole output structure is also incorporated for enhanced power switch protection.
Undervoltage lockout thresholds for the UCCx813-[2,3,4,5] devices are different from the previous generation of UCx84[2,3,4,5] PWM controllers. The thresholds are optimized for two groups of applications: off-line power supplies and DC-DC converters. See Table 1 for the specific thresholds for each device.
DEVICE | VON (V) | VOFF (V) |
---|---|---|
UCCx813-0 | 7.2 | 6.9 |
UCCx813-1 | 9.4 | 7.4 |
UCCx813-[2,4] | 12.5 | 8.3 |
UCCx813-[3,5] | 4.1 | 3.6 |
The UCCx813-[2,4] feature typical UVLO thresholds of 12.5 V for turnon and 8.3 V for turnoff, providing 4.3 V of hysteresis.
For low voltage inputs, which include battery and 5-V applications, the UCCx813-[3,5] turn on at 4.1 V and turn off at 3.6 V with 0.5 V of hysteresis.
The UCCx813-[0,1] have UVLO thresholds optimized for automotive and battery applications.
During UVLO, the device draws approximately 100 µA of supply current. Once VCC crosses the turnon threshold, the IC supply current increases typically to about 500 µA, over an order of magnitude lower than bipolar counterparts. Figure 11 indicates the supply current behavior at the relative UVLO turnon and turnoff thresholds, not including average OUT current.
The self-biasing, active-low clamp circuit shown in Figure 12 eliminates the potential for problematic MOSFET turnon. As the PWM output voltage rises while in UVLO, the P-channel device drives the larger N-channel switch ON, which clamps the output voltage low. Power to this circuit is supplied by the externally rising gate voltage, so full protection is available regardless of the device's supply voltage during undervoltage lockout.
The traditional 5-V band-gap-derived reference voltage of the UC3842 family can be also found on the UCCx813-[0,1,2,4] devices. However, the reference voltage of the UCCx813-[3,5] devices is 4 V. This change was necessary to facilitate operation with input supply voltages below 5 V. Many of the reference voltage specifications are similar to the UC3842 devices although the test conditions have been changed, indicative of lower-current PWM applications. Similar to their bipolar counterparts, the BiCMOS devices internally pull the reference voltage low during UVLO, which can be used as a logic status indication.
The 4-V reference voltage on the UCCx813-[3,5] is derived from the supply voltage (VVCC) and requires about 0.5 V of headroom to maintain regulation. Whenever VVCC is below approximately 4.5 V, the reference voltage also drops outside of its specified range for normal operation. The relationship between VVCC and VREF during this excursion is shown in Figure 14.
The noninverting input to the error amplifier is tied to one-half of the controller's reference voltage (VREF). This input is 2 V on the UCCx813-[3,5] and 2.5 V on the higher reference voltage parts: the UCCx813-[0,1,2,4].
The UCCx813-x oscillator generates a sawtooth waveform on RC. The rise time is set by the time constant of RT and CT. The fall time is set by CT and an internal transistor on-resistance of approximately 130 Ω. During the fall time, the output is OFF and the maximum duty cycle is reduced below 50% or 100%, depending on the part number. Larger values for the timing capacitor increase the discharge time and reduce the maximum duty cycle and frequency slightly, as seen in Figure 5 and Figure 6 .
The oscillator section of the UCCx813-x BiCMOS family has few similarities to the UC3842 type — other than single-pin programming. It does still use a resistor to the reference voltage and capacitor to ground to program the oscillator frequency up to 1 MHz. Timing component values must be changed because a much lower charging current is desirable for low-power operation. Several characteristics of the oscillator have been optimized for high-speed, noise-immune operation. The oscillator peak-to-peak amplitude has been increased to 2.45 V typical versus 1.7 V on the UC3842 family. The lower oscillator threshold has been dropped to approximately 0.2 V while the upper threshold remains fairly close to the original 2.8 V at approximately 2.65 V.
Discharge current of the timing capacitor has been increased to nearly 20-mA peak as opposed to roughly 8 mA. This can be represented by approximately 130 Ω in series with the discharge switch to ground. The higher current is necessary to achieve brief dead times and high duty cycles with high-frequency operation. Practical applications can use these devices to a 1-MHz switching frequency.
Synchronization of these PWM controllers is best obtained by the universal technique shown in Figure 19. The device oscillator is programmed to free-run at a frequency about 20% lower than that of the synchronizing frequency. A brief positive pulse is applied across the 50-Ω resistor to force synchronization. Typically, a 1-V amplitude pulse of 100-ns width is sufficient for most applications.
The controller can also be synchronized to a pulse-train applied directly to the oscillator RC pin. The device internally pulls low at this node once the upper oscillator threshold is crossed. This 130-Ω impedance to ground remains active until the voltage on RC is lowered below 0.2 V. External synchronization circuits must accommodate these conditions.
Maximum duty cycle is higher for these devices than for their UC384[2,3,4,5] predecessors. This is primarily due to the higher ratio of timing capacitor discharge-to-charge current, which can exceed one hundred-to-one in a typical BiCMOS application. Attempts to program the oscillator maximum duty cycle much below the specified range, by adjusting the timing component values of RT and CT, must be avoided. There are two reasons to refrain from this design practice. First, the device's high discharge current would necessitate higher charging current than necessary for programming, defeating the purpose of low power operation. Second, a low-value timing resistor may prevent the capacitor from discharging to the lower threshold and initiating the next switching cycle.
Dead time is the term used to describe the ensured OFF time of the PWM output during each oscillator cycle. It is used to ensure that even at maximum duty cycle, there is enough time to reset the magnetic circuit elements, and prevent saturation. The dead time of the UCCx813-x PWM family is determined by the internal 130-Ω discharge impedance and the timing capacitor value. Larger capacitance values extend the dead time whereas smaller values results in higher maximum duty cycles for the same operating frequency. A curve for dead time versus timing capacitor values is provided in Figure 20. Further increasing the dead time is possible by adding a low-value resistor between the RC pin and the timing components, as shown in Figure 21. The dead time increases with increasing discharge resistor value to about 470 Ω as indicated from the curve in Figure 22. Higher resistances must be avoided as they can decrease the dead time and reduce the oscillator peak-to-peak amplitude. Sinking too much current (1 mA) by reducing RT will freeze the oscillator OFF by preventing discharge to the lower comparator threshold voltage of 0.2 V. Adding this discharge control resistor has several impacts on the oscillator programming. First, it introduces a DC offset to the capacitor during the discharge interval – but not the charging interval of the timing cycle, thus lowering the usable peak-to-peak timing capacitor amplitude. Because of the reduced peak-to-peak amplitude, the exact value of CT may require adjustment to obtain the correct oscillator frequency. One alternative is keep the same value timing capacitor and adjust both the timing and discharge resistor values because these are readily available in finer numerical increments.
RT = 20 kΩ |
A 100-ns leading-edge-blanking interval is applied to the current-sense input circuitry of the UCCx813-x devices. This internal feature eliminates the requirement for an external resistor-capacitor filter network to suppress the switching spike associated with turnon of the power MOSFET. This 100-ns period should be adequate for most switch-mode designs but can be lengthened by adding an external R/C filter. The 100-ns leading edge blanking is also applied to the overcurrent fault comparator in addition to the cycle-by-cycle current-limiting PWM function.
The PWM comparator has two inputs; one is from the current sense input, the other input is the attenuated error-amplifier output (COMP) that has a diode and two resistors in series to ground. The diode in this network is used to ensure that zero duty-cycle can be reached. Whenever the E/A output falls below a diode forward voltage drop, no current flows in the resistor divider and the PWM input goes to zero, resulting in zero pulse width.
Under certain conditions, the leading-edge-blanking circuitry can lead to an output pulse of minimum width equal to the blanking interval. This occurs when the COMP is slightly higher than a diode forward voltage drop of about 0.5 V, such that the attenuated COMP input to the PWM comparator allows an output pulse to start. If the attenuated COMP level commands a peak current whose pulse width would fall within the leading-edge-blanking interval, the output will remain ON until the blanking interval is finished and the peak current will be higher than desired by the COMP level. The usual result is that the converter output voltage rises, increasing the error, and COMP is driven lower than the diode drop which then produces zero pulse width. Cycle-skipping may result as the output voltage rises and falls around this minimum pulse-width condition.
A 1-V (typical) cycle-by-cycle current limit threshold is incorporated into the UCCx813-x family. The 100-ns leading-edge-blanking interval is applied to this current-limiting circuitry. The blanking overrides the current-limit comparator output to prevent the leading-edge switch noise from triggering a current-limit function. Propagation delay from the current-limit comparator to the output is typically 70 ns. This high-speed path minimizes power semiconductor dissipation during an overload by abbreviating the ON time.
For increased efficiency in the current-sense circuitry, the circuit shown in Figure 26 can be used. Resistors RA and RB bias the actual current-sense resistor voltage up, allowing a smaller current sense amplitude to be used. This circuitry provides current-limiting protection with lower power-loss current sensing.
The example shown uses a 200-mV full-scale signal at the current sense resistor. Resistor RB biases this up by approximately 700 mV to match the 0.9-V minimum specification of the current-limit comparator of the IC. The value of resistor RA changes with the specific IC used, due to the different reference voltages. The resistor values should be selected for minimal power loss. For example, a 50-µA bias current sets RB = 13 kΩ, and RA = 75 kΩ for UCCx813-[0,1,2,4] or RA = 56 kΩ for UCCx813-[3,5] devices.
A separate overcurrent comparator within the UCCx813-x devices handles operation into a short-circuited or severely overloaded power supply output. This overcurrent comparator has a 1.5-V threshold and is also gated by the leading edge blanking signal to prevent false triggering. Once triggered, the overcurrent comparator uses the internal soft-start capacitor to generate a delay before retry is attempted. Often referred to as hiccup, this delay time is used to significantly reduce the input and dissipated power of the main converter and switching components. Full-cycle soft start ensures that there is a predictable delay of greater than 3 ms between successive attempts to operate during fault conditions. The circuit shown in Figure 28 and the timing diagram in Figure 29 show how the IC responds to a severe fault, such as a saturated inductor. When the peak current fault is first detected, the internal soft-start capacitor instantly discharges and stays discharged until the fault clears. At the same time, the PWM output is turned off and held off. When the fault clears, the capacitor slowly charges and allows the error amp output (COMP) to rise. When COMP gets high enough to enable the output, another fault occurs, latching off the PWM output, but the soft-start capacitor still continues to rise to 4 V before being discharged and permitting start of a new cycle. This means that for a severe fault, successive retries is spaced by the time required to fully charge the soft-start capacitor. TI recommends low leakage transformer designs in high-frequency applications to activate the overcurrent protection feature. Otherwise, the switch current may not ramp up sufficiently to trigger the overcurrent comparator within the leading edge blanking duration. This condition would cause continual cyclical triggering of the cycle-by-cycle current limit comparator but not the overcurrent comparator. This would result in brief high power dissipation durations in the main converter at the switching frequency. The intent of the overcurrent comparator is to reduce the effective retry rate under these conditions to a few milliseconds, thus significantly lowering the short-circuit power dissipation of the converter.
Internal soft starting of the PWM output is accomplished by gradually increasing the error amplifier (E/A) output voltage at COMP. When used in current-mode control, this implementation slowly raises the peak switch current each PWM cycle in succession, forcing a controlled start-up. In voltage-mode (duty-cycle) control, this feature continually widens the pulse width.
Soft-start is performed within the UCCx813-x devices by clamping the E/A amplifier output (COMP) to the voltage on an internal soft-start capacitor (CSS), which is charged by a current source. CSS is discharged following an undervoltage lockout transition or if the reference voltage is below a minimum value for normal operation. Additionally, discharge of CSS occurs whenever the overcurrent protection comparator is triggered by a fault. The soft-start clamp circuitry is overridden once CSS charges above the voltage commanded by the error amplifier for normal PWM operation.
Slope compensation can be added in all current-mode control applications to cancel the peak-to-average current error. Slope compensation is necessary in applications with duty-cycles exceeding 50%, but also improves performance in those below 50%. Primary current is sensed using resistor RCS in series with the converter switch. The timing resistor can be broken up into two series resistors to bias up an NPN voltage-follower, as shown in Figure 32. This is required to provide ample compliance for slope compensation at the beginning of a switching cycle, especially with continuous-current converters. The voltage follower drives the slope compensating programming resistor (RSC) to provide a slope-compensating current into CF.
The UCCx813-x family of high-speed, low-power current-mode PWM controllers has the following functional modes.
During this operation mode, the IC controls the power converter into the voltage-mode or current-mode control, regulates the output voltage or current through the converter duty cycle. The regulation can be achieve through the integrated error amplifier or external feedback circuitry.
During the system start-up, VVCC voltage starts to rise from 0 V. Before the VCC voltage reaches its corresponding turn-on threshold, the IC operates in UVLO mode. In this mode, REF pin voltage is not generated. When VVCC is above 1 V and below the turnon threshold, the REF pin is actively pulled low through a 5-kΩ resistor. This way, VREF can be used as a logic signal to indicate UVLO mode.
Once VCC voltage rises above the UVLO level, or the device comes out of a fault mode, it enters the soft-start mode. During soft-start, the internal soft-start capacitor CSS clamps the error amplifier output voltage, forcing it to rise slowly. This in turn controls the power converter peak current to rise slowly, reducing the voltage and current stress to the system. The UCCx813-x family has a fixed built-in soft-start time at 4 ms.
A separate overcurrent comparator within the UCCx813-x devices handles operation into a short-circuited or severely overloaded power supply output. This overcurrent comparator has a 1.5-V threshold and is also gated by the leading-edge-blanking signal to prevent false triggering. When the fault is first detected, the internal soft-start capacitor instantly discharges and stays discharged until the fault clears. At the same time, the PWM output is turned off and held off. This is often referred to as hiccup. This delay time is used to significantly reduce the input and dissipated power of the main converter and switching components. Full-cycle soft-start insures that there is a predictable delay of greater than 3 milliseconds between successive attempts to operate during fault. When the fault clears, the capacitor slowly charges and allows the error amp output (COMP) to rise. When COMP gets high enough to enable the output, another fault occurs, latching off the PWM output, but the soft-start capacitor still continues to rise to 4 V before being discharged and permitting start of a new cycle. This means that for a severe fault, successive retries are spaced by the time required to fully charge the soft-start capacitor.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The UCCx813-x controllers are peak-current-mode (PCM) pulse-width modulators (PWM). These controllers have an onboard amplifier and can be used in isolated and nonisolated power supply design. There is an onboard totem-pole gate driver capable of delivering up to ±1 A of peak current. These controllers are capable of operating at switching frequencies up to 1 MHz.
Figure 33 illustrates a typical circuit diagram for an AC-DC converter using the UCC2813-0 in a peak-current-mode-controlled flyback application.
Use the parameters in Table 2 to review the design of a 12-V, 48-W offline flyback converter using the UCC2813-0 PWM controller.
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERSTICS | ||||||
VIN | Input voltage (RMS) | 85 | 265 | V | ||
fLINE | Line frequency | 47 | 63 | Hz | ||
OUTPUT CHARACTRSTICS | ||||||
VOUT | Output voltage | 11.75 | 12 | 12.25 | V | |
Vripple | Output ripple voltage | 120 | mVPP | |||
IOUT | Output current | 4 | 4.33 | A | ||
Vtran | Output transient | Output voltage measured under 0-A to 4-A load step | 11.75 | 12.25 | V | |
SYSTEM CHARACTRSTICS | ||||||
η | Max load efficiency | 85% |
The design starts with selecting an appropriate bulk capacitor.
The primary-side bulk capacitor is selected based on the input power level and on the desired minimum bulk voltage level. The bulk capacitor value can be calculated by Equation 5.
where
Based on this equation, to achieve 75-V minimum bulk voltage, assuming 85% converter efficiency and 47-Hz minimum line frequency, the bulk capacitor must be larger than 127 µF. 180 µF was chosen in the design, considering the typical tolerance of bulk capacitors.
The transformer design starts with selecting a suitable switching frequency. Generally the switching frequency selection is based on a tradeoff between the converter size and efficiency, based on the simple Flyback topology. Normally, higher switching frequency results in smaller transformer size. However, the switching loss is increased and hurts the efficiency. Sometimes, the switching frequency is selected to avoid certain communication bands to prevent noise interference with the communication. The frequency selection is beyond the scope of this data sheet.
The switching frequency is targeted for 110 kHz, to minimize the transformer size. At the same time, because EMI regulations start to limit conducted noise at 150 kHz, choosing 110-kHz switching frequency can help to reduce the EMI filter size.
The transformer turns ratio can be selected based on the desired MOSFET voltage rating and diode voltage rating. Because maximum input voltage is 265 V AC, the peak bulk voltage can be calculated by Equation 6.
To minimize the cost of the system, a popular 650-V MOSFET is selected. Considering the design margin and extra voltage ringing on the MOSFET drain, the reflected output voltage must be less than 120 V. The transformer turns ratio can be selected by Equation 7.
The transformer inductance selection is based on the continuous conduction mode (CCM) condition. Higher inductance would allow the converter to stay in CCM longer. However, it tends to increase the transformer size. Normally, the transformer magnetizing inductance is selected so that the converter enters CCM operation at about 50% load at minimum line voltage. This would be a tradeoff between the transformer size and the efficiency. In this particular design, due to the higher output current, it is desired to keep the converter deeper in CCM and minimize the conduction loss and output ripple. The converter enters CCM operation at about 10% load at minimum bulk voltage.
The inductor can be calculated as Equation 8.
In this equation, the switching frequency is 110 kHz. Therefore, the transformer inductance must be about 1.7 mH. 1.5 mH is chosen as the magnetizing inductance value.
The auxiliary winding provides the bias power for UCC2813-0 normal operation. The auxiliary winding voltage is the output voltage reflected to the primary side. It is desired to have higher reflected voltage so that the IC can quickly get energy from the transformer and make start-up under heavy load easier. However, higher reflected voltage makes the IC consume more power. Therefore, a tradeoff is required.
In this design, the auxiliary winding voltage is selected to be the same as the output voltage so that it is above the UVLO level but keeps the IC and driving loss low. Therefore, the auxiliary winding to the output winding turns ratio is selected by Equation 9.
Based on calculated primary inductance value and the switching frequency, the current stress of the MOSFET and diode can be calculated.
The peak current of the MOSFET is calculated by Equation 10.
The MOSFET peak current is 1.425 A.
The RMS current of the MOSFET can be calculated as Equation 11.
where
The MOSFET RMS current is 0.75 A. With less than 0.9-Ω on-resistance, IRFB9N65A is selected as the primary-side MOSFET.
The diode peak current is the reflected MOSFET peak current on the secondary side.
The diode voltage stress is the output voltage plus the reflected input voltage. The voltage stress on the diode can be calculated by Equation 14.
Considering the ringing voltage spikes and voltage derating, the diode voltage rating must be higher than 50 V.
The diode average current is the output current (4 A), so 48CTQ060-1, with 60-V rating and 40-A average current capability, is selected.
The output capacitor is selected based on the output voltage ripple requirement. In this design, 0.1% voltage ripple is assumed. Based on the 0.1% ripple requirement, the capacitor value can be selected based on Equation 15.
Considering the tolerance and temperature effect, together the ripple current rating of the capacitors, 3 parallel 680-µF capacitors are selected for the output.
After the basic power stage is designed, the surrounding controller components can be selected.
The current sensing network consists of RCS, RCSF, CCSF, and optional RP. Typically, the direct current sense signal contains a large-amplitude leading-edge spike associated with the turn-on of the main power MOSFET, reverse recovery of the output rectifier, and other factors including charging and discharging of parasitic capacitances. Therefore, CCSF and RCSF form a low-pass filter that provides additional immunity beyond the internal blanking time to suppress the leading edge spike. For this converter, CCSF is chosen to be 270 pF to provide enough filtering.
Without RP, RCS sets the maximum peak current in the transformer primary based on the maximum amplitude of CS pin, 1 V. To achieve 1.425-A primary side peak current, a 0.75-Ω resistor is chosen for RCS.
The high current-sense threshold helps to provide better noise immunity but the current-sense loss is increased. The current-sense loss can be minimized by injecting an offset voltage into the current-sense signal. RP and RCSF form a resistor-divider network from the current-sense signal to the device’s reference voltage to offset the current-sense voltage. This technique still achieves current-mode control with cycle-by-cycle overcurrent protection. To calculate required offset value (Voffset), use Equation 16.
RG is the gate driver resistor for the power switch, QA. The selection of this resistor value must be done in conjunction with EMI compliance testing and efficiency testing. Larger RG slows down the turn-on and turn-off of the MOSFET. Slower switching speed reduces EMI but also increases the switching loss. A tradeoff between switching loss and EMI performance must be carefully performed. For this design, 10 Ω was chosen as the gate driver resistor.
The precision 5-V reference voltage at REF is designed to perform several important functions. The reference voltage is divided down internally to 2.5 V and connected to the error amplifier’s noninverting input for accurate output voltage regulation. Other duties of the reference voltage are to set internal bias currents and thresholds for functions such as the oscillator upper and lower thresholds along with the overcurrent limiting threshold. Therefore, the reference voltage must be bypassed with a ceramic capacitor (CVREF), and 1-µF, 16-V ceramic capacitor was selected for this converter. Placement of this capacitor on the physical printed-circuit board layout must be as close as possible to the respective REF and GND pins.
The internal oscillator uses a timing capacitor (CT) and a timing resistor (RT) to program operating frequency and maximum duty cycle. The operating frequency can be programmed based the curves in Figure 3, where the timing resistor can be found once the timing capacitor is selected. The selection of timing capacitor also affects the maximum duty cycle provided in Figure 5. It is best for the timing capacitor to have a flat temperature coefficient, typical of most COG or NPO type capacitors. For this converter, 1000 pF and 13.6 kΩ were selected for CT and RT to operate at 110-kHz switching frequency.
At start-up, the IC gets its power directly from the high voltage bulk, through a high-voltage resistor RH. The selection of start-up resistor is the tradeoff between power loss and start-up time. The current flowing through RH at minimum input voltage must be higher than the VCC current under UVLO condition (0.2 mA at its maximum value). A 300-kΩ resistor is chosen as the result of the tradeoff.
After VCC is charged up above the UVLO turnon threshold, UCC2813-0 starts to operate and consumes full operating current. At the beginning, because the output voltage is low, VCC cannot get energy from the auxiliary winding. The VCC capacitor is required to hold enough energy to prevent its voltage drop below UVLO during the start-up time, until the output reaches high enough. A larger capacitor holds more energy but slows down the start-up time. In this design, a 120-µF capacitor is chosen to provide enough energy for the start-up purpose.
Feedback compensation, also called closed-loop control, reduces or eliminates steady-state output voltage error, reduces the sensitivity to parametric changes, changes the gain or phase of a system over some desired frequency range, reduces the effects of small-signal load disturbances and noise on system performance, and creates a stable system. This section describes how to compensate an isolated Flyback converter with the peak-current-mode control.
The first step in compensating a fixed-frequency flyback is to verify if the converter operates in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance (LP) is greater than the inductance for DCM-CCM boundary mode operation, called the critical inductance (LPcrit), then the converter operates in CCM. LPcrit is calculated with Equation 17.
For loads greater than 10% of PMAX over the entire input voltage range, the selected primary inductance has value larger than the critical inductance. Therefore, the converter operates in CCM and the compensation loop requires design based on CCM flyback equations.
The current-to-voltage conversion is done externally with the ground-referenced current-sense resistor (RCS) and the internal resistor divider sets up the internal current-sense gain, ACS = 1.65. The IC technology allows tight control of the resistor-divider ratio, regardless of the actual resistor value variations.
The DC open-loop gain (GO) of the fixed-frequency voltage control loop of a peak-current-mode control CCM flyback converter shown in Figure 33 is approximated by first using the output load (ROUT), the primary to secondary turns ratio (NPS), and the maximum duty cycle (D) as shown in Equation 18.
where
For this design, a converter with an output voltage (VOUT) of 12 V, and 48 W relates to an output load (ROUT) equal to 3 Ω at full load.
At minimum input bulk voltage of 75 V DC, the duty cycle reaches its maximum value of 0.615. The current sense resistance (RCS) is 0.75 Ω and a primary to secondary turns-ratio (NPS) is 10. The open-loop gain calculates to 14.95 dB.
A CCM flyback transfer function has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero to the power stage, and the frequency of this zero (fESRz) is calculated with Equation 22.
The fESRz zero for a capacitance bank of three 680-µF capacitors (for a total output capacitance of 2040 µF) and a total ESR of 13 mΩ is located at 6 kHz.
CCM flyback converters have a zero in the right-half plane (RHP) of their transfer function. RHP zero has the same 20 dB/decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location (fRHPz) in Equation 23 is a function of the output load, the duty cycle, the primary inductance (LP), and the primary to secondary side turns ratio (NPS).
RHP zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest RHP zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zero frequency (fRHPz) is equal to 7.65 kHz at maximum duty cycle (full load).
The power stage has one dominant pole (ωP1) which is in the region of interest, located at a lower frequency (fP1) which is related to the duty cycle (D), the output load, and the output capacitance. There is also a double pole (fP2) located at half the switching frequency of the converter. These poles are frequencies calculated with Equation 24 and Equation 25.
Subharmonic oscillation is the large signal instability that can occur in CCM flyback converters when duty cycles extend beyond 50%. The subharmonic oscillation increases the output voltage ripple and sometimes it even limits the power handling capability of the converter. Slope compensation to the CS signal is a technique used to eliminate the instability.
Ideally, the target of slope compensation is to achieve quality coefficient (QP = 1) at half of the switching frequency. The QP is calculated by Equation 26.
where
where
The optimal goal of the slope compensation is to achieve QP equal to 1, which means MC must be 2.128 when D reaches it maximum value of 0.615.
The inductance current slope at the CS pin is calculated by Equation 28.
The compensation slope is calculated by Equation 29.
The compensation slope is added into the system through RRAMP and RCSF. A series capacitor (CRAMP) is selected to approximate a high-frequency short circuit. Choose CRAMP as 10 nF as the starting point, and make adjustments if required. RRAMP and RCSF form a voltage divider to scale the RC pin ramp voltage and inject the slope compensation into CS pin. Choose RRAMP much larger than the RT resistor so that it does not affect the frequency setting very much. In this design, RRAMP is selected as 24.9 kΩ. The RC pin ramp slope is calculated with Equation 30.
To achieve 46.3 mV/µs compensation slope, RCSF resistor is calculated with Equation 31.
The power stage open-loop gain and phase can be plotted as a function of frequency. The total open-loop transfer function, as a function of frequency, can be characterized by Equation 32.
where
The open-loop gain and phase Bode plots are graphed accordingly (see Figure 34 and Figure 35).
For good transient response, the bandwidth of the finalized design must be as wide as possible. The bandwidth of a CCM flyback (fBW) is limited to ¼ of the RHP-zero frequency, or approximately 1.9 kHz using Equation 33.
The gain of the open-loop power stage at fBW is equal to –22.4 dB and the phase at fBW is equal to –87°. First step is to choose the output voltage-sensing resistor values. The output sensing resistors are selected based on the allowed power consumption and in this case, 1 mA of sensing current is assumed.
The TL431 is used as the feedback amplifier. Given its 2.5-V reference voltage, the voltage-sensing dividers RFBU and RFBB can be selected with Equation 34 and Equation 35.
Next step is to put the compensator zero fCZ at 190 Hz, which is 1/10 of the target crossover frequency. Choose CZ as a fixed value of 10 nF and choose the zero resistor value according to Equation 36.
Next, place a pole at the lower of RHP-zero or the ESR-zero frequencies. Based previous analysis, the RHP zero is at 7.65 kHz and the ESR zero is at 6 kHz, so the pole of the compensation loop should be put at 6 kHz. This pole can be added through the primary side error amplifier. RFB and CFB provide the necessary pole. Choosing RFB as 10 kΩ, CFB is calculated by Equation 37.
Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 38.
where
The only remaining unknown value required in this equation is RLED. The entire loop gain must be equal to 1 at the crossover frequency. RLED is calculated accordingly as 1.62 kΩ.
The final closed-loop Bode plots are shown in Figure 36 and Figure 37. The converter achieves approximately 2-kHz crossover frequency and approximately 70° of phase margin.
TI recommends checking the loop stability across all the corner cases, including component tolerances, to ensure system stability.
100 V/div | 2 µs/div |
CH1: output voltage AC coupled | 200 mV/div | |
CH4: output current | 1 A/div | 5 ms/div |
5 V/div | 2 ms/div |
100 V/div | 2 µs/div |
100 mV/div | 10 µs/div | |