JAJSTU7H August   2007  – July 2024 CDCE937 , CDCEL937

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: CLK_IN
    7. 5.7 Timing Requirements: SDA/SCL
    8. 5.8 EEPROM Specification
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Register Maps
    1. 8.1 SDA/SCL Configuration Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

13 Revision History

Changes from Revision G (October 2016) to Revision H (July 2024)

  • ドキュメント全体にわたって表、図、相互参照の採番方法を更新Go

Changes from Revision F (March 2010) to Revision G (October 2016)

  • 「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加Go
  • 「アプリケーション」を変更Go
  • Changed Thermal Resistance Junction to Ambient, RθJA, values in Thermal Information From: 89 (0 lfm), 75 (150 lfm), 74 (200 lfm), 74 (250 lfm), and 69 (500 lfm) To: 89.04Go
  • Deleted Input Capacitance figureGo

Changes from Revision E (October 2009) to Revision F (March 2010)

  • Added PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096 foot to PLL1, PLL2, and PLL3 Configure Register TableGo
  • Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4Go
  • Changed under Example, fifth row, N", 2 places TO N'Go

Changes from Revision D (September 2009) to Revision E (October 2009)

  • Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments sales or marketing representative for more informationGo

Changes from Revision C (January 2009) to Revision D (September 2009)

  • Added Note 3: SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions tableGo

Changes from Revision B (December 2007) to Revision C (January 2009)

  • Changed Generic Configuration Register table SLAVE_ADR default value From: 00b To: 01bGo

Changes from Revision A (September 2007) to Revision B (December 2007)

  • Changed Terminal Functions Table - the pin numbers to correspond with pin outs on the packageGo
  • Added note to PWDN description to Generic Configuration Register tableGo
  • Changed Generic Configuration Register table RID default From: 0h To: XbGo

Changes from Revision * (August 2007) to Revision A (September 2007)

  • データシートのステータスを次のように変更：「製品プレビュー」から「量産データ」に変更Go