SBOA442 March   2021 TMP107 , TMP107-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2CAN and RS-485 Physical Layers
  4. 3TMP107-Q1 Over the CAN Bus
  5. 4TMP107-Q1 Over the RS-485 Bus
  6. 5Test Setup
  7. 6Test Results
  8. 7Conclusion
  9. 8References

Test Results

Figure 6-1 and Figure 6-2 show real waveforms for the CAN to SMAART wire interface converter circuit. The host microcontroller reads out temperature from three sensors at 9600 bps.

GUID-20201218-CA0I-MPM6-XWBJ-KWFWZZ83XCTG-low.png
Channel1: CANL, Channel2: CANH
Channel3: I/O, Channel4: DIR
Figure 6-1 Real Waveforms for the CAN to SMAART wire™ Interface Converter Circuit
GUID-20201218-CA0I-GVLJ-XJGJ-VJSHBFXWZ4H9-low.png
Channel1: CANL, Channel2: CANH
Channel3: I/O, Channel4: DIR
Figure 6-2 Real Waveforms for the CAN to SMAART wire™ Interface Converter Circuit

Figure 6-3 shows real waveforms for the RS-485 to SMAART wire interface converter without the timing capacitor C9. Note that during the TMP107-Q1 sensor transmitting the RS-485 bus switches only between the logic-low and idle state. The communication works because the receive data output pin R of the SN65HVC485 transceiver on the receiving side returns logic high for the properly-terminated bus in the idle state.

GUID-20201218-CA0I-LKKR-5Q2N-ZHGZMGGNF5SV-low.pngFigure 6-3 Real Waveforms for the RS-485 to SMAART wire™ Interface Converter Circuit Without
the Timing Capacitor C8

Adding the capacitor C8 (68 nF) extends the pulse and forces the RS-485 bus remaining in the active state for longer time as shown in the Figure 6-4. The control signal DIR returns to zero during transmitting the stop bit over the bus.

GUID-20201218-CA0I-FCWT-R9TC-ZQJRVKPHNBNG-low.pngFigure 6-4 Real Waveforms for the RS-485 to SMAART wire™ Interface Converter Circuit With
the Timing Capacitor C8 (68 nF)

Figure 6-5 and Figure 6-6 show further improvement with the timing capacitor C8 and the diode D1. The diode from the timing capacitor to the I/O signal converts the circuit into re-triggable single-shot timer. At least every start bit re-triggers the timing circuitry and extends the period for which the DIR signal keeps the bus in active state.

GUID-20201218-CA0I-R5QP-4FVJ-DDGJKGB54R2F-low.pngFigure 6-5 Real Waveforms for the RS-485 to SMAART wire™ Interface Converter Circuit With
the Timing Capacitor C8 and Diode D1
GUID-20201218-CA0I-ZMRR-85SH-DTWP3MK444F7-low.pngFigure 6-6 Real Waveforms for the RS-485 to SMAART wire™ Interface Converter Circuit With
the Timing Capacitor C8 and Diode D1 (Detail)