SLAAEH0 November   2023 AFE781H1 , AFE782H1 , AFE881H1 , AFE882H1 , DAC161P997 , DAC161S997 , DAC7750 , DAC7760 , DAC8740H , DAC8741H , DAC8742H , DAC8750 , DAC8760 , DAC8771 , DAC8775

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to the HART Protocol
    1. 1.1 Different Forms of the HART Protocol
    2. 1.2 HART as an Enhancement to the 4-20 mA Loop
    3. 1.3 The HART FSK Signal
    4. 1.4 HART Configurations
    5. 1.5 HART Protocol Structure
      1. 1.5.1 HART Communication
      2. 1.5.2 HART Bytes
      3. 1.5.3 HART Data Frame Structure
        1. 1.5.3.1 HART Start Byte
        2. 1.5.3.2 HART Device Addressing
        3. 1.5.3.3 HART Commands
  5. 2HART Protocol and Test Specifications
    1. 2.1 The OSI Protocol Model
    2. 2.2 HART Protocol Specifications
    3. 2.3 HART Test Specifications
  6. 3TI HART Enabled Devices
    1. 3.1 TI DACs with HART Connections
    2. 3.2 TI HART Modems
  7. 4Conclusion
  8. 5References

4 Conclusion

The HART protocol is an enhancement to the 4-20mA loop that adds digital communication to an established analog system. This communication protocol is widely-used for factory automation and control. This application note describes the basics of the HART protocol, showing the implementation in existing 4-20mA loops, the FSK as part of the physical transmission, and the data structure. The HART protocol specifications and the HART protocol test specifications guide developers in creating HART enabled devices through the registration process with FieldComm Group. TI produces many DAC devices that can easily integrate HART signals into FA&C applications.