SLAAEI9 December 2023 MSPM0C1103 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1228
Table 3-9 gives a brief comparison between STM8 and MSPM0 devices.
STM8 | MSPM0 | ||||
---|---|---|---|---|---|
Operation Mode | Description | Operation Mode | Description | ||
Run mode | CPU and peripherals run normally after a system or power reset. | RUN | 0 | MCLK and CPUCLK run from a fast clock source (SYSOSC) | |
Low power run mode | CPU and peripherals run with a low speed oscillator (LSI or LSE). All interrupts must be masked. | 1 | MCLK and CPUCLK run from LFCLK (at 32 kHz). | ||
2 | |||||
Wait mode | CPU operation stops. Oscillator remains enable. Selected peripherals keep running. Wait mode is entered from Run mode by executing a WFI or WFE instruction. | SLEEP | 0 | CPU operation stops. SYSOSC remains enable. LFOSC remains enable. MCLK run from a fast clock source (SYSOSC). | |
1 | CPU operation stops. SYSOSC remains enable. LFOSC remains enable. MCLK run from LFCLK. | ||||
Low power wait mode | CPU operation stops. Low speed oscillator remains enable. Selected peripherals keep running. This mode is entered when executing a Wait for event in low power run mode. All interrupts must be masked. | 2 | CPU operation stops. SYSOSC remains disable. LFOSC remains enable. MCLK run from LFCLK. | ||
Active-halt mode(STM8S) | CPU operation stops. Oscillators are disable except LSI or HSE. Almost all the peripherals are stopped except AWU. the MVR regulator is powered on. | STOP(2) | 0 | CPU operation stops. Status of SYSOSC is retained(1). LFOSC remains enable. ULPCLK is limited to 4 MHz. PD0 is enabled and PD1 is disabled. And analog peripherals such as ADC can operate. | |
1 | Same as STOP0, with the SYSOSC and ULPCLK gear shifted to 4 MHz. | ||||
Active-halt mode with MVR auto power off(STM8S) | CPU operation stops. Oscillators are disable except LSI only. Almost all the peripherals are stopped except AWU. the MVR regulator is powered off. | 2 | CPU operation stops. SYSOSC is disable. ULPCLK runs at 32 kHz. PD0 is enabled and PD1 is disabled. | ||
Active-halt mode (not STM8S families) | CPU operation stops. Oscillators are disable except LSI or LSE. Almost all the peripherals are stopped except RTC, AWU, and so forth. The voltage regulator is at low power mode. | STANDBY | 0 | CPU operation stops. SYSOSC is disable. All PD0 peripherals receive the ULPCLK and LFCLK. | |
Halt mode | CPU operation stops. Oscillators are disable(3). Almost all the peripherals are stopped(3). The voltage regulator is at low power mode. | 1 | Similar to STANDBY0, with only TIMG0/1 receiving ULPCLK or LFCLK. | ||
N/A | N/A | SHUTDOWN | No clocks are available and device is shut down. |
STM8L05xx devices have five low power modes: Wait mode, Low power run mode, Low power wait mode, Active-halt mode and Halt mode. STM8L001xx and STM8L101xx devices have three low power modes: Wait mode, Active-halt mode and Halt mode. STM8 series have four low power modes: Wait mode, Active-halt mode, Active-halt with MVR auto power off, and Halt mode.