SLUA560D June 2011 – March 2022 UCC28950 , UCC28950-Q1 , UCC28951 , UCC28951-Q1
The synchronous FETs are chosen based on current and voltage ratings; as well as, power dissipation to meet the designs efficiency goals. This can be a trial an error process. We selected an evaluated a 75-V, 120-A FETs, from Fairchild, part number FDP032N08 to see if they could be used for synchronous FETs QE and QF to hit our efficiency goals. After estimating the total FET losses and power budget it was determined that these FETs could be used in this design.
Calculate average FET COSS (COSS_QE_AVG) based on the data sheet parameters for COSS (COSS_SPEC), and drain to source voltage where COSS_SPEC was measured (Vds_spec), and the maximum drain to source voltage in the design (VdsQE) that will be applied to the FET in the application.
Voltage across FET QE and QF when they are off:
Voltage where FET COSS is specified and tested in the FET data sheet:
Specified output capacitance from FET data sheet:
Average QE and QF COSS [2]:
QE and QF RMS current:
To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First the gate charge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gate charge at the end of the miller plateau (QEMILLER_MAX) for the given VDS.
Maximum gate charge at the end of the miller plateau:
Minimum gate charge at the beginning of the miller plateau:
The FETs in this design were driven with UCC27324 setup to drive 4-A (IP) of gate drive current.
Estimated FET Vds rise and fall time:
Estimate QE and QF FET Losses (PQE):
Recalculate the power budget and check remaining power budget to hit efficency goal.